參數(shù)資料
型號： HI5812
廠商： Intersil Corporation
英文描述： CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold(CMOS 12位片內(nèi)帶跟蹤和保持電路的A/D轉(zhuǎn)換器)
中文描述： 20微秒的CMOS，12位，采樣的A / D轉(zhuǎn)換器內(nèi)部跟蹤和保持的CMOS（12位片內(nèi)帶跟蹤和保持電路的的A / D轉(zhuǎn)換器）
文件頁數(shù)： 10/16頁
文件大?。?/td> 366K
代理商： HI5812
10
Theory of Operation
HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that
uses capacitor-charge balancing to successively approximate
the analog input. A binarily weighted capacitor network forms
the A/D heart of the device. See the block diagram for the
HI5812.
The capacitor network has a common node which is
connected to a comparator. The second terminal of each
capacitor is individually switchable to the input, V
REF
+ or
V
REF
-.
During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input
and the comparator is being auto-balanced at the capacitor
common node.
During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
connected to the V
REF
+ terminal; and the remaining
capacitors to V
REF
-. The capacitor-common node, after the
charges balance out, will indicate whether the input was
above
1
/
2
of (V
REF
+ - V
REF
-). At the end of the fourth
period, the comparator output is stored and the MSB
capacitor is either left connected to V
REF
+ (if the comparator
was high) or returned to V
REF
-. This allows the next
comparison to be at either
3
/
4
or
1
/
4
of (V
REF
+ - V
REF
-).
At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
capacitor either left at V
REF
+ or at V
REF
-.
At the end of the 15th period, when the LSB (D0) capacitor is
tested, (D0) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data-ready output goes active. The conversion cycle is
now complete.
Analog Input
The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5
μ
A and 20pF.
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have
low enough impedance to dissipate the current spike by the
end of the tracking period as shown in Figure 18. The
amount of charge is dependent on supply and input
voltages. The average current is also proportional to clock
frequency.
As long as these current spikes settle completely by end of
the signal acquisition period, converter accuracy will be
preserved. The analog input is tracked for 3 clock cycles.
With an external clock of 750kHz the track period is 4
μ
s.
TABLE 1. PIN DESCRIPTIONS
PIN NO.
NAME
DESCRIPTION
1
DRDY
Output flag signifying new data is available.
Goes high at end of clock period 15. Goes low
when new conversion is started.
2
D0
Bit 0 (Least Significant Bit, LSB).
3
D1
Bit 1.
4
D2
Bit 2.
5
D3
Bit 3.
6
D4
Bit 4.
7
D5
Bit 5.
8
D6
Bit 6.
9
D7
Bit 7.
10
D8
Bit 8.
11
D9
Bit 9.
12
V
SS
D10
Digital Ground (0V).
13
Bit 10.
14
D11
Bit 11 (Most Significant Bit, MSB).
15
OEM
Three-State Enable for D4-D11. Active low input.
16
V
AA
-
V
AA
+
V
IN
V
REF
+
Analog Ground, (0V).
17
Analog Positive Supply. (+5V) (See text.)
18
Analog Input.
19
Reference Voltage Positive Input, sets 4095
code end of input range.
20
V
REF
-
Reference Voltage Negative Input, sets 0 code
end of input range.
21
STRT
Start Conversion Input Active Low, recognized
after end of clock period 15.
22
CLK
CLK Input or Output. Conversion functions are
synchronized to positive going edge. (See
text.)
23
OEL
Three-State Enable for D0 D3. Active Low Input.
24
V
DD
Digital Positive Supply (+5V).
20mA
10mA
0mA
5V
0V
5V
0V
I
IN
CLK
DRDY
200ns/DIV.
CONDITIONS: V
DD
= V
AA
+ = 5.0V, V
REF
+ = 4.608V,
V
IN
= 4.608V, CLK = 750kHz, T
A
= 25
o
C
FIGURE 18. TYPICAL ANALOG INPUT CURRENT
HI5812
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相關代理商/技術參數(shù)
參數(shù)描述
HI5812_05 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold
HI5812JIB 功能描述:ADC 12BIT 50KSPS 1.5LSB 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:-
HI5812JIBS2548 制造商:Intersil Corporation 功能描述:
HI5812JIBZ 功能描述:ADC 12BIT 50KSPS 1.5LSB 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:-
HI5812JIBZ-T 功能描述:ADC 12BIT SAMPL TRK&HOLD 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:-
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