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| 型號： | HEF4557BT |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1-to-64 bit variable length shift register |
| 封裝： | HEF4557BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4557BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 148K |
| 代理商： | HEF4557BT |
HEF4557B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 16 December 2009
8 of 16
NXP Semiconductors
HEF4557B
1-to-64 bit variable length shift register
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
The set-up, hold, and recovery times vary with the minimum number of bits selected. For intermediate numbers not specified, interpolate
as shown in
Table 9
.
[2]
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care
t
rec
recovery time
MR input;
L1 to L32 = LOW;
see
Figure 5
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
[2]
500
250
150
110
70
60
250
125
75
50
30
25
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MR input;
L32 = HIGH
f
max
maximum
frequency
see
Figure 5
2.5
7
10
5
14
20
Table 8.
V
SS
= 0 V; T
amb
= 25
°
C; for test circuit see
Figure 6
; unless otherwise specified.
Symbol Parameter
Conditions
Dynamic characteristics
…continued
V
DD
Extrapolation formula
Min
Typ
Max
Unit
Table 9.
Length control inputs
L1
L2
L
L
H
L
Interpolation table
[1]
Minimum number of
bits selected
Set-up, hold, and
recovery times
Example: t
rec
minimum, V
DD
= 5 V
L4
L
L
L8
L
L
L16
L
L
L32
L
L
1
2
see
Table 8
(interpolate in 6
equal steps)
500 ns
435 ns
X
X
X
X
X
H
X
X
X
X
L
H
X
X
X
L
L
H
X
X
L
L
L
H
X
L
L
L
L
H
3
5
9
370 ns
305 ns
240 ns
175 ns
110 ns
17
33
see
Table 8
Table 10.
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
≤
20 ns; T
amb
= 25
°
C.
Symbol
Parameter
V
DD
Typical formula for P
D
(
μ
W)
P
D
dynamic power
dissipation
10 V
P
D
= 15000
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
15 V
P
D
= 37000
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
Dynamic power dissipation P
D
where:
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
Σ
(f
o
×
C
L
) = sum of the outputs.
5 V
P
D
= 3500
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
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