參數(shù)資料
型號(hào): HEF4543BP
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: BCD to 7-segment latch-decoder-driver
封裝: HEF4543BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4543BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁數(shù): 8/16頁
文件大?。?/td> 99K
代理商: HEF4543BP
HEF4543B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
8 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
12. Waveforms
t
h
hold time
D
n
to LE;
see
Figure 6
5 V
10 V
15 V
5 V
10 V
15 V
0
15
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
15
20
60
30
20
0
5
t
W
pulse width
pin LE HIGH;
minimum width;
see
Figure 6
30
15
10
Table 7.
V
SS
= 0 V; T
amb
= 25
°
C; For test circuit see
Figure 7
;unless otherwise specified.
Symbol
Parameter
Conditions
Dynamic characteristics
…continued
V
DD
Extrapolation formula
[1]
Min
Typ
Max
Unit
Table 8.
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
°
C.
Symbol
Parameter
V
DD
Typical formula for P
D
(
μ
W)
P
D
dynamic power
dissipation
10 V
P
D
= 10400
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
15 V
P
D
= 33000
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
Dynamic power dissipation P
D
where:
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
Σ
(C
L
×
f
o
) = sum of the outputs.
5 V
P
D
= 2200
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
Conditions: D3 = LOW and D0 = D1 =HIGH.
Fig 5.
Propagation delays and output transitions times
001aaj496
V
I
V
I
V
M
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
TLH
t
THL
t
PLH
t
PLH
t
PLH
V
M
V
M
10 %
V
M
V
M
V
SS
V
I
V
SS
V
OH
V
OL
V
SS
V
I
V
SS
LT
BL
Qg
LE
90 %
D2
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