參數(shù)資料
型號(hào): HEF4521BT
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 24-stage frequency divider and oscillator
封裝: HEF4521BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4521BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁數(shù): 8/17頁
文件大小: 106K
代理商: HEF4521BT
HEF4521B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 5 November 2009
8 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
13. Waveforms
Table 9.
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
°
C.
Symbol
Parameter
V
DD
Typical formula for P
D
(
μ
W)
P
D
dynamic power
dissipation
10 V
P
D
= 5100
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
15 V
P
D
= 13050
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
Dynamic power dissipation P
D
where:
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
Σ
(C
L
×
f
o
) = sum of the outputs.
5 V
P
D
= 1200
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
a. Pulse widths, maximum frequency, recovery and transition times and A2 to Qn propagation delays
b. A1 to Y1, MR to Qn and Qn to Qn + 1 propagation delays
Measurement points are given in
Table 10
.
The logic levels V
OH
and V
OL
are typical output voltage levels that occur with the output load.
Waveforms showing measurement of dynamic characteristics
Fig 5.
001aae712
A2 input
1/f
max
t
W
t
rec
t
t
t
t
t
PHL
t
PLH
V
OH
V
I
MR input
0 V
0 V
V
I
V
OL
V
M
10 %
90 %
t
W
V
M
Qn output
001aak015
V
M
V
I
0 V
A1 input
Y1 propagation delays
Qn to Qn + 1 propagation delays
V
OH
V
OL
Y1 output
t
PLH
V
M
t
PHL
V
OH
V
OL
Qn output
V
OH
V
OL
Qn + 1 output
V
M
t
PLH
V
M
t
PHL
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