參數(shù)資料
型號: HEF4521BP
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 24-stage frequency divider and oscillator
封裝: HEF4521BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4521BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁數(shù): 5/17頁
文件大?。?/td> 106K
代理商: HEF4521BP
HEF4521B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 5 November 2009
5 of 17
NXP Semiconductors
HEF4521B
24-stage frequency divider and oscillator
8.
Functional Test
A test function has been included to reduce the test time required to test all 24 counter
stages. This test function divides the counter into three 8-stage sections by connecting
V
SS1
to V
DD
and V
DD1
to V
SS
. 255 counts are loaded into each of the 8-stage sections in
parallel via A2 (connected to Y2). All flip-flops are now at a HIGH level. The counter is now
returned to the normal 24-stage in series configuration by connecting V
SS1
to V
SS
and
V
DD1
to V
DD
. Entering one more pulse into input A2 will cause the counter to ripple from
an all HIGH state to an all LOW state.
[1]
H = HIGH voltage level; L = LOW voltage level;
= HIGH to LOW transition.
9.
Limiting values
[1]
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
°
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
°
C.
[2]
Table 4.
Inputs
MR
H
Functional test sequence
Control terminals
Y2
L
Outputs
Q18 to Q24
L
Remarks
A2
L
V
SS1
V
DD
V
DD1
V
SS
counter is in three 8-stage sections in parallel mode; A2 and Y2
are interconnected (Y2 is now input); counter is reset by MR.
255 pulses are clocked into A2, Y2. The counter advances on
the LOW to HIGH transition.
L
see
Remarks
column
L
H
H
see
Remarks
column
L
L
L
V
DD
V
SS
H
L
L
L
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
H
H
H
V
SS1
is connected to V
SS
.
the input A2 is made HIGH.
V
DD1
is connected to V
DD
; Y2 is now made floating and
becomes an output; the device is now in the 2
24
mode.
counter ripples from an all HIGH state to an all LOW state.
L
V
SS
V
DD
L
Table 5.
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
V
DD
supply voltage
I
IK
input clamping current
V
I
input voltage
I
OK
output clamping current
I
I/O
input/output current
I
DD
supply current
T
stg
storage temperature
T
amb
ambient temperature
P
tot
total power dissipation
Limiting values
Conditions
Min
0.5
-
0.5
-
-
-
65
40
Max
+18
±
10
V
DD
+ 0.5
±
10
±
10
±
100
+150
+85
750
500
100
Unit
V
mA
V
mA
mA
mA
°
C
°
C
mW
mW
mW
V
I
<
0.5 V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5 V or V
O
> V
DD
+ 0.5 V
to any supply terminal
DIP16 package
SO16 package
per output
[1]
-
[2]
-
P
power dissipation
-
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