參數(shù)資料
型號(hào): HEF4516BT
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Binary up-down counter
封裝: HEF4516BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4516BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁(yè)數(shù): 10/17頁(yè)
文件大小: 174K
代理商: HEF4516BT
HEF4516B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 11 November 2011
10 of 17
NXP Semiconductors
HEF4516B
Binary up/down counter
11. Waveforms
Table 8.
P
D
can be calculated from the formulas shown. V
SS
= 0 V; C
L
= 50 pF; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol
Parameter
V
DD
Typical formula for P
D
(
W)
P
D
dynamic power
dissipation
10 V
P
D
= 4500
f
i
+
(f
o
C
L
)
V
DD2
15 V
P
D
= 11200
f
i
+
(f
o
C
L
)
V
DD2
Dynamic power dissipation P
D
Where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
(f
o
C
L
) = sum of the outputs.
5 V
P
D
= 1000
f
i
+
(f
o
C
L
)
V
DD2
Measurement points are given in
Table 9
.
Fig 6.
Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP
001aae672
CP input
V
I
V
SS
V
SS
V
SS
V
I
V
I
CE input
UP/DN input
t
W
V
M
t
su
V
M
t
h
t
su
t
h
t
su
t
h
V
M
Measurement points are given in
Table 9
.
Fig 7.
Waveforms showing PL and MR minimum pulse widths and recovery times, and Dn to PL set-up and hold
times
001aae673
CP input
V
I
V
SS
V
SS
V
SS
V
SS
V
I
V
I
V
I
PL input
Dn input
V
M
t
W
t
rec
V
M
MR input
t
rec
V
M
t
W
V
M
t
h
t
su
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