參數(shù)資料
型號(hào)： HEF4052BTT
廠商： NXP SEMICONDUCTORS
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Dual 4-channel analog multiplexer-demultiplexer
中文描述： DUAL 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16
封裝： 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁(yè)數(shù)： 13/22頁(yè)
文件大?。?/td> 199K
代理商： HEF4052BTT
HEF4052B_7
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 — 26 March 2010
13 of 22
NXP Semiconductors
HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
11.2 Additional dynamic parameters
[1]
f
i
is biased at 0.5 V
DD
; V
I
= 0.5V
DD
(p-p).
11.2.1
Test circuits
Table 11.
V
SS
= V
EE
= 0 V; T
amb
= 25
°
C.
Symbol
THD
Additional dynamic characteristics
Parameter
total harmonic distortion
Conditions
see
Figure 17
; R
L
= 10 k
Ω
; C
L
= 15 pF;
channel ON; V
I
= 0.5V
DD
(p-p);
f
i
= 1 kHz
V
DD
5 V
10 V
15 V
5 V
10 V
15 V
10 V
Typ
Max
-
-
-
-
-
-
Unit
%
%
%
MHz
MHz
MHz
dB
[1]
0.25
[1]
0.04
[1]
0.04
f
(
3dB)
3 dB frequency response
see
Figure 18
; R
L
= 1 k
Ω
; C
L
= 5 pF;
channel ON; V
I
= 0.5V
DD
(p-p)
[1]
13
[1]
40
[1]
70
α
iso
isolation (OFF-state)
see
Figure 19
; f
i
= 1 MHz; R
L
= 1 k
Ω
;
C
L
= 5 pF; channel OFF;
V
I
= 0.5V
DD
(p-p)
digital inputs to switch; see
Figure 20
;
R
L
= 10 k
Ω
; C
L
= 15 pF;
E or Sn = V
DD
(square-wave)
between switches; see
Figure 21
;
f
i
= 1 MHz; R
L
= 1 k
Ω
;
V
I
= 0.5V
DD
(p-p)
[1]
50
-
V
ct
crosstalk voltage
10 V
50
-
mV
Xtalk
crosstalk
10 V
[1]
50
-
dB
Table 12.
P
D
can be calculated from the formulas shown; V
EE
= V
SS
= 0 V; t
r
= t
f
≤
20 ns; T
amb
= 25
°
C.
Symbol
Parameter
V
DD
Typical formula for P
D
(
μ
W)
P
D
dynamic power
dissipation
10 V
P
D
= 6100
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
15 V
P
D
= 15600
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
Dynamic power dissipation P
D
where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
Σ
(C
L
×
f
o
) = sum of the outputs.
5 V
P
D
= 1300
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
Fig 17. Test circuit for measuring total harmonic
distortion
Fig 18. Test circuit for measuring frequency response
D
001aak638
V
SS
fi
RL
CL
V
SS
= V
EE
S1 and S2
E
nZ
V
DD
or V
SS
V
DD
nYn
dB
001aak639
V
SS
fi
RL
CL
V
SS
= V
EE
S1 and S2
E
nZ
V
DD
or V
SS
V
DD
nYn
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