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參數(shù)資料
| 型號(hào)： | HEF4046BT |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | Phase-locked loop |
| 封裝： | HEF4046BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4046BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week |
| 文件頁(yè)數(shù)： | 6/19頁(yè) |
| 文件大?。?/td> | 178K |
| 代理商： | HEF4046BT |
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HEF4046B_4
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 5 January 2010
6 of 19
NXP Semiconductors
HEF4046B
Phase-locked loop
Figure 6
shows the state diagram for phase comparator 2. Each circle represents a state
of the comparator. The number at the top, inside each circle, represents the state of the
comparator, while the logic state of the signal and comparator inputs are represented by a
‘0’ for a logic LOW or a ‘1’ for a logic HIGH, and they are shown in the left and right bottom
of each circle.
The transitions from one to another result from either a logic change at the signal input (S
representing SIG_IN) or the comparator input (C representing COMP_IN). A positive-
going and a negative-going transition are shown by an arrow pointing up or down
respectively.
The state diagram assumes, that only one transition on either the signal input or
comparator input occurs at any instant.
States 3, 5, 9 and 11 represent the output condition when the p-type driver is ON.
States 2, 4, 10 and 12 determine the condition when the n-type driver is ON.
States 1, 6, 7 and 8 represent the condition when the output is in its high-impedance
OFF state; i.e. both p and n-type drivers are OFF, and the PCP_OUToutput is HIGH.
The condition at output PCP_OUT for all other states is LOW.
S
↑
: 0 to 1 transition at the signal input SIG_IN.
C
↓
: 1 to 0 transition at the comparator input COMP_IN.
Fig 6.
State diagram for comparator 2
001aae631
1
0
0
6
1
1
n
0
0
8
1
0
4
0
0
2
0
1
3
1
0
5
0
0
7
0
1
9
1
1
11
0
1
10
1
1
12
1
0
C
S
S
C
C
C
S
C
S
C
S
C
S
S
C
C
C
n-type driver ON
n and p-type
drivers are OFF
state number of
the comparator
logic state of
comparator input (pin 3)
logic state of
signal input (pin 14)
p-type driver ON
S
C
C
S
S
S
S
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HEF4046BT,652 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| HEF4046BT,653 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| HEF4046BT,653-CUT TAPE | 制造商:NXP 功能描述:HEF4000 Series 4.5 - 15.5 V Phase-Locked Loop - SOT109-1 |
| HEF4046BT | 制造商:NXP Semiconductors 功能描述:IC 4000 LOCMOS SMD 4046 SOIC16 |
| HEF4046BT/S400,118 | 制造商:NXP Semiconductors 功能描述:- Tape and Reel |
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