- 您現(xiàn)在的位置：買賣IC網 > PDF目錄384400 > HEF4046BT (NXP Semiconductors N.V.) Phase-locked loop PDF資料下載
參數(shù)資料
| 型號： | HEF4046BT |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Phase-locked loop |
| 封裝： | HEF4046BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4046BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 178K |
| 代理商： | HEF4046BT |
HEF4046B_4
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 5 January 2010
4 of 19
NXP Semiconductors
HEF4046B
Phase-locked loop
the frequency range of input signals on which the PLL will lock if it was initially out of lock.
The frequency lock range (2f
L
) is defined as the frequency range of input signals on which
the loop will stay locked if it was initially in lock. The capture range is smaller or equal to
the lock range.
With phase comparator 1, the range of frequencies over which the PLL can acquire lock
(capture range) depends on the low-pass filter characteristics and this range can be made
as large as the lock range. Phase comparator 1 enables the PLL system to remain in lock
in spite of high amounts of noise in the input signal. A typical behavior of this type of
phase comparator is that it may lock onto input frequencies that are close to harmonics of
the VCO center frequency. Another typical behavior is that the phase angle between the
signal and comparator input varies between 0
°
and 180
°
, and is 90
°
at the center
frequency.
Figure 3
shows the typical phase-to-output response characteristic.
Figure 4
shows the typical waveforms for a PLL with a f
0
locked phase comparator 1.
(1) Average output voltage.
Fig 3.
Signal-to-comparator inputs phase difference for comparator 1
001aae628
V
DD(1)
0.5V
DD
0
0
°
90
°
180
°
Fig 4.
Typical waveforms for phase-locked loop with a f
0
locked phase comparator 1
SIG_IN
VCO_IN
001aae629
V
DD
V
SS
PC1_OUT
COMP_IN
VCO_OUT
相關PDF資料 |
PDF描述 |
|---|---|
| HEF4047BP | Monostable-astable multivibrator |
| HEF4047BT | Monostable-astable multivibrator |
| HEF4049BP | Hex inverting buffers |
| HEF4049BT | Hex inverting buffers |
| HEF4050BT | Hex non-inverting buffers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HEF4046BT,652 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| HEF4046BT,653 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| HEF4046BT,653-CUT TAPE | 制造商:NXP 功能描述:HEF4000 Series 4.5 - 15.5 V Phase-Locked Loop - SOT109-1 |
| HEF4046BT | 制造商:NXP Semiconductors 功能描述:IC 4000 LOCMOS SMD 4046 SOIC16 |
| HEF4046BT/S400,118 | 制造商:NXP Semiconductors 功能描述:- Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。