參數(shù)資料
型號(hào)： HEF4046BT
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： Phase-locked loop
封裝： HEF4046BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4046BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁(yè)數(shù)： 10/19頁(yè)
文件大?。?/td> 178K
代理商： HEF4046BT
HEF4046B_4
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 5 January 2010
10 of 19
NXP Semiconductors
HEF4046B
Phase-locked loop
[1]
Over the recommended component range.
[2]
The offset voltage is equal to the input voltage on pin VCO_IN minus the output voltage on pin SF_OUT.
12. Design information
Δ
f/f
relative frequency
variation
for VCO see
Figure 13
and
14
R1 > 10 k
Ω
R1 > 400 k
Ω
R1 = M
Ω
VCO _OUT output
5 V
10 V
15 V
5 V
10 V
15 V
-
-
-
-
-
-
0.50
0.25
0.25
50
50
50
10
6
-
-
-
-
-
-
% Hz
% Hz
% Hz
%
%
%
M
Ω
δ
duty factor
R
in
Source follower
V
offset
input resistance
for pin VCO_IN
offset voltage
R
L
= 10 k
Ω
; VCO_IN at 0.5V
DD
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
[2]
-
1.7
2.0
2.1
1.5
1.7
1.8
0.3
1.0
1.3
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
%
%
%
-
-
-
-
-
-
-
-
R
L
= 50 k
Ω
; VCO_IN at 0.5V
DD
Δ
f/f
relative frequency
variation
VCO output; R
L
> 50 k
Ω
; see
Figure 13
Zener diode
V
Z
R
dyn
working voltage
dynamic resistance
I
Z
= 50
μ
A
For internal Zener diode; I
Z
= 1 mA
-
-
-
-
7.3
25
-
-
V
Ω
Table 6.
V
SS
= 0 V; T
amb
= 25
°
C; C
L
= 50 pF; input transition times
≤
20 ns.
Symbol
Parameter
Dynamic characteristics
…continued
Conditions
V
DD
Min
Typ
Max
Unit
Table 7.
Test
VCO adjusts with no signal on SIG_IN
Design information
Using phase comparator 1
VCO in PLL system adjusts
to center frequency (f
0
)
90
°
at center frequency (f
0
),
approaching 0
°
and 180
°
at the
ends of the lock range (2f
L
)
yes
high
the frequency range of the input signal on which the loop will stay locked if it
was initially in lock; 2f
L
= full VCO frequency range = f
max
f
min
the frequency range of the input signal on which the loop will lock if it was
initially out of lock
depends on low-pass
filter characteristics; 2f
c
< 2f
L
the frequency of the VCO when VCO_IN at 0.5V
DD
Using phase comparator 2
VCO in PLL system adjusts to
minimum frequency (f
min
)
always 0
°
in lock
(positive-going edges)
Phase angle between SIG_IN and COMP_IN
Locks on harmonics of center frequency
Signal input noise rejection
Lock frequency range (2f
L
)
no
low
Capture frequency range (2f
c
)
2f
c
= 2f
L
Center frequency (f
0
)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HEF4046BT,652 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
HEF4046BT,653 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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