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參數(shù)資料
| 型號： | HEF4027BT |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK flip-flop |
| 封裝： | HEC4027BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week 6, 2004,;HEC4027BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week 6 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 103K |
| 代理商： | HEF4027BT |
HEF4027B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 10 October 2011
7 of 14
NXP Semiconductors
HEF4027B
Dual JK flip-flop
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
t
t
is the same as t
TLH
and t
THL
.
[2]
12. Waveforms
f
max
maximum
frequency
CP input;
J = K = HIGH;
see
Figure 5
5 V
10 V
15 V
4
12
15
8
25
30
-
-
-
MHz
MHz
MHz
Table 7.
V
SS
= 0 V; T
amb
= 25
C; for test circuit see
Figure 7
; unless otherwise specified.
Symbol Parameter
Conditions
Dynamic characteristics
…continued
V
DD
Extrapolation formula
[1]
Min
Typ
Max
Unit
Table 8.
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol
Parameter
V
DD
Typical formula for P
D
(
W)
P
D
dynamic power
dissipation
10 V
P
D
= 4500
f
i
+
(f
o
C
L
)
V
DD2
15 V
P
D
= 13200
f
i
+
(f
o
C
L
)
V
DD2
Dynamic power dissipation P
D
Where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
(f
o
C
L
) = sum of the outputs.
5 V
P
D
= 900
f
i
+
(f
o
C
L
)
V
DD2
V
OH
and V
OL
are typical output voltages levels that occur with the output load.
Measurement points are given in
Table 9
.
Fig 4.
Waveforms showing rise, fall and transition times and propagation delays
Measurement points are given in
Table 9
.
Fig 5.
Waveforms showing set-up and hold times and minimum clock pulse width
001aah863
SD, CD or CP
INPUT
V
I
0 V
V
OH
V
OL
Q or Q
OUTPUT
V
M
V
M
t
PLH
t
PHL
90 %
90 %
10 %
10 %
t
r
t
TLH
t
THL
t
f
001aae596
CP INPUT
J,K INPUT
t
W
V
M
V
M
1/f
max
t
su
t
h
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HEF4027BT,652 | 功能描述:觸發(fā)器 DUAL JK F/F EDGE-TRG RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| HEF4027BT,653 | 功能描述:觸發(fā)器 DUAL JK FLIP-FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| HEF4027BT,653-CUT TAPE | 制造商:NXP 功能描述:HEF4000 Series 5 - 15 V Dual Jk Flip-Flop - SOT109-1 |
| HEF4027BT | 制造商:NXP Semiconductors 功能描述:IC 4000 LOCMOS SMD 4027 SOIC16 |
| HEF4027BT652 | 制造商:NXP Semiconductors 功能描述:IC DUAL JK FLIP FLOP 30NS SOIC-16 |
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