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參數資料
| 型號： | HEF40175BTT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad D-type flip-flop |
| 中文描述： | 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 4.4 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16 |
| 文件頁數： | 6/15頁 |
| 文件大?。?/td> | 143K |
| 代理商： | HEF40175BTT |
HEF40175B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 3 May 2011
6 of 15
NXP Semiconductors
HEF40175B
Quad D-type flip-flop
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formula shown (C
L
in pF).
Table 8.
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
≤
20 ns; T
amb
= 25
°
C.
Symbol Parameter
V
DD
P
D
dynamic power dissipation
5 V
10 V
15 V
t
PLH
LOW to HIGH
propagation delay
CP to Qn or Qn;
see
Figure 5
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
[1]
43 ns + (0.55 ns/pF) C
L
19 ns + (0.23 ns/pF) C
L
17 ns + (0.16 ns/pF) C
L
43 ns + (0.55 ns/pF) C
L
19 ns + (0.23 ns/pF) C
L
17 ns + (0.16 ns/pF) C
L
10 ns + (1.00 ns/pF) C
L
9 ns + (0.42 ns/pF) C
L
6 ns + (0.28 ns/pF) C
L
-
-
-
-
-
-
-
-
-
70
30
25
70
30
25
60
30
20
30
10
5
5
140
65
45
140
65
50
120
60
40
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MR to Qn;
see
Figure 5
t
t
transition time
see
Figure 5
[1]
t
su
set-up time
Dn to CP;
see
Figure 5
60
20
15
+25
10
10
90
35
25
80
30
20
t
h
hold time
Dn to CP;
see
Figure 5
0
0
t
W
pulse width;
CP input LOW;
minimum pulse
width see
Figure 5
45
15
10
40
15
10
MR input LOW;
minimum pulse
width see
Figure 5
t
rec
recovery time
MR input;
see
Figure 5
0
0
0
5
30
20
15
11
30
45
f
max
maximum frequency
15
20
Table 7.
V
SS
= 0 V; T
amb
= 25
°
C; for test circuit see
Figure 6
; unless otherwise specified.
Symbol Parameter
Conditions
Dynamic characteristics
…continued
V
DD
Extrapolation formula
Min
Typ
Max
Unit
Dynamic power dissipation P
D
Typical formula for P
D
(
μ
W)
P
D
= 2000
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
P
D
= 8400
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
P
D
= 22500
×
f
i
+
Σ
(f
o
×
C
L
)
×
V
DD2
where:
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
Σ
(f
o
×
C
L
) = sum of the outputs.
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| HEF40175BTT,118 | 功能描述:觸發(fā)器 18V 160ns TSSOP16 RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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