參數(shù)資料
型號(hào)： HE84760B
廠商： King Billion Electronics Co., Ltd.
英文描述： 8-bit Micro-controller
中文描述： 8位微控制器
文件頁(yè)數(shù)： 40/51頁(yè)
文件大?。?/td> 487K
代理商： HE84760B
21.3.
Interrupt & Identification Register
KING BILLION ELECTRONICS CO., LTD
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HE84760B
HE80004 Series
June 29, 2005
This specification is subject to change without notice. Please contact sales person for the latest version before use.
40
V1.0
This high nibble of IEIR register allows to enable/disable interrupt generation by the UART, the low
nibble ID[2..0] of IEIR register is used to identify the source of interrupts.
Address
0x02h
RBRI: Receiver Buffer Register Interrupt (1 = Enable, 0 = Disable), related to ID[1] bit.
THRI: Transmitter Hold Register Interrupt (1 = Enable, 0 = Disable), related to ID[0] bit.
RLSI: Receiver Line Status Interrupt (1 = Enable, 0 = Disable), related to ID[2] bit.
Name
IEIR
Bit 7
0
-
Bit 6
RLSI
R/W
Bit 5
THRI
R/W
Bit 4
RBRI
R/W
Bit 3
0
-
Bit 2
ID2
R
Bit 1
ID1
R
Bit 0
ID0
R
Reset Value
“0000_0000”
The following table shows the related interrupt sources, user can read the ID[2:0] to retrieve what is the
current highest priority of pending interrupts. The ID[2:0] bits will be cleared when user read the related
registers. For example, when an interrupt happened and the content of ID[2:0] is “101”, this means that
LRS error and THR empty happen; user can read the LSR register to clear the ID[2] bit and ID[0] bit can
also be cleared by reading the IEIR or writing data into THR register.
Level
None
Highest
Second
IEIR Bit [2:0]
0 0 0
1 0 0
0 1 0
Source of Interrupt
Interrupt Reset Control
None
Reading LSR register to clear ID[2]
Reading RBR register to clear ID[1]
Reading IEIR register or Writing
THR register to clear ID[0]
None
LSR error flags (OE/PE/FE/BI)
LSR receiver data ready flag (DR)
Third
0 0 1
LSR flag THR Empty (THRE)
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