參數(shù)資料
型號： HDM8515P
廠商： Hynix Semiconductor Inc.
英文描述： Operational Amplifier (Op-Amp) IC; Number of Amplifiers:4; Package/Case:14-DIP; Op Amp Type:Low Power; Single Supply Voltage Min (+V):3V; Dual Supply Voltage Max (+/- V):16V; Amplifier Type:Operational; Mounting Type:Through Hole
中文描述： 的DVB /決策支持系統(tǒng)兼容接收器
文件頁數(shù)： 6/75頁
文件大?。?/td> 272K
代理商： HDM8515P
6
LIST OF TABLES
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
...............................................................................................................9
T
ABLE
2: DC C
HARACTERISTICS
.................................................................................................................................9
T
ABLE
3: D
EMODULATOR
S
PECIFICATIONS
...........................................................................................................10
T
ABLE
4: AC C
HARACTERISTICS
...............................................................................................................................10
T
ABLE
5: I
NTEL
80C88A R
EAD
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
= 1)................................................11
T
ABLE
6: I
NTEL
80C88A W
RITE
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
= 1).............................................12
T
ABLE
7: I
NTEL
8051 R
EAD
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
= 1)......................................................13
T
ABLE
8: I
NTEL
8051 W
RITE
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
= 1)...................................................14
T
ABLE
9: M
OTOROLA
R
EAD
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
=0)....................................................15
T
ABLE
10: M
OTOROLA
W
RITE
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
=0).................................................16
T
ABLE
11: O
UTPUT
T
IMING
.......................................................................................................................................17
T
ABLE
12: E
XAMPLE OF
A
CQUISITION
T
IMING
.....................................................................................................27
T
ABLE
13: I2C S
LAVE
A
DDRESS
..................................................................................................................................47
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