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參數(shù)資料
| 型號： | HDM8515 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | ANALOG IC - DATASHEET REFERENCE |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | LQFP-100 |
| 文件頁數(shù)： | 5/75頁 |
| 文件大小： | 272K |
| 代理商： | HDM8515 |
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LIST OF FIGURES
F
IGURE
1: T
OP
L
EVEL
B
LOCK
D
IAGRAM
....................................................................................................................7
F
IGURE
2: I
NPUT
D
ATA
T
IMING
D
IAGRAM
.............................................................................................................10
F
IGURE
3: I
NTEL
80C88A R
EAD
T
IMING
D
IAGRAM
...............................................................................................11
F
IGURE
4: I
NTEL
80C88A W
RITE
T
IMING
D
IAGRAM
.............................................................................................12
F
IGURE
5: I
NTEL
8051 R
EAD
T
IMING
D
IAGRAM
.....................................................................................................13
F
IGURE
6: I
NTEL
8051 W
RITE
T
IMING
D
IAGRAM
...................................................................................................14
F
IGURE
7: M
OTOROLA
R
EAD
T
IMING
D
IAGRAM
....................................................................................................15
F
IGURE
8: M
OTOROLA
W
RITE
T
IMING
D
IAGRAM
.................................................................................................16
F
IGURE
9: O
UTPUT
T
IMING
D
IAGRAM FOR
N
ORMAL
P
ARALLEL
.......................................................................17
F
IGURE
10: O
UTPUT
T
IMING
D
IAGRAM FOR
N
ORMAL
S
ERIAL
...........................................................................17
F
IGURE
11: O
UTPUT
T
IMING
D
IAGRAM FOR
R
EGULATED
P
ARALLEL
...............................................................18
F
IGURE
12: O
UTPUT
T
IMING
D
IAGRAM FOR
R
EGULATED
S
ERIAL
.....................................................................18
F
IGURE
13: ADC B
LOCK
D
IAGRAM
............................................................................................................................ 20
F
IGURE
14 D
EMODULATOR
B
LOCK
D
IAGRAM
........................................................................................................21
F
IGURE
15: N
OISE
M
EASUREMENT
C
IRCUIT
...........................................................................................................23
F
IGURE
16: N
OISE
A
CCUMULATOR AS A FUNCTION OF
SNR
AND
T
IME
............................................................ 24
F
IGURE
17: V
ITERBI
D
ECODER
...................................................................................................................................25
F
IGURE
18: R
EED
S
OLOMON
D
ECODER
....................................................................................................................29
F
IGURE
19: T
YPICAL
S
ET
T
OP
B
OX
D
EMODULATOR
............................................................................................ 35
F
IGURE
20: M
ECHANICAL
C
ONFIGURATION
...........................................................................................................38
F
IGURE
21: M
ECHANICAL
C
ONFIGURATION
...........................................................................................................40
F
IGURE
22: A
NALOG
P
IN
C
ONNECTION
....................................................................................................................41
F
IGURE
23: CLOCK GENERATION CIRCUIT...........................................................................................................41
F
IGURE
24: I2C W
RITE TO THE
HDM8515..............................................................................................................46
F
IGURE
25: I2C R
EAD FROM THE
HDM8515............................................................................................................47
F
IGURE
A1: S
YMBOL
T
IMING
R
ECOVERY
T
RANSIENT
R
ESPONSE
.......................................................................67
F
IGURE
A2: C
ARRIER
P
HASE
R
ECOVERY
T
RANSIENT
R
ESPONSE
........................................................................68
F
IGURE
A3: C
ARRIER
P
HASE
R
ECOVERY
T
RANSIENT
R
ESPONSE WITH
L
OW
SNR..........................................69
F
IGURE
A4: A
DJACENT
C
HANNEL
I
NTERFERENCE OF
10
D
B, 1.35 S
PACING
....................................................72
F
IGURE
A5: P
ERFORMANCE WITH INTERFERER AT DIFFERENT CARRIER SPACINGS
.....................................73
F
IGURE
A6: P
ERFORMANCE WITH
+10
D
B I
NTERFERER
......................................................................................74
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