- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄384397 > HDM8513AT (Hynix Semiconductor Inc.) Darlington Bipolar Transistor; Power Dissipation:175W; Package/Case:TO-3; Mounting Type:Through Hole; Current Rating:20A; Voltage Rating:500V PDF資料下載
參數(shù)資料
| 型號(hào)： | HDM8513AT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | Darlington Bipolar Transistor; Power Dissipation:175W; Package/Case:TO-3; Mounting Type:Through Hole; Current Rating:20A; Voltage Rating:500V |
| 中文描述： | 的DVB /決策支持系統(tǒng)兼容接收器 |
| 文件頁(yè)數(shù)： | 24/67頁(yè) |
| 文件大?。?/td> | 261K |
| 代理商： | HDM8513AT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)當(dāng)前第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)
24
3.4 Viterbi Decoder
The Viterbi decoder accepts 3 bit soft decision samples of the in-phase (I) and quadrature (Q)
components of the received signal. Once QPSK lock has been achieved, the decoder searches for
the correct code rate, starting with rate 3/4, then proceeding to rate 2/3, 5/6, 7/8 and finally rate
1/2. Each of the possible synchronization phases at each rate is tested as well as the two
possible carrier phase ambiguity conditions. Polarity reversal is corrected in the word
synchronization logic. Viterbi lock is achieved when the trellis traceback algorithm converges, on
the average, within a prescribed number of symbols.
Although the algorithm automatically tests for carrier phase ambiguity, there is no provision to
automatically correct for phase reversal. Phase reversal can occur if the receiver chain, consisting
of an LNB and the tuner, provides an odd number of high side frequency translation operations. A
system may be required to operate with different LNBs, some of which provide phase reversal.
This condition may be corrected by the host processor, which can set a bit in the down converter
to correct for phase reversal.
The Viterbi decoder employs the radix two algorithm. The output buffer reserializes the data which
is made available, along with the Viterbi data clock as external signals. These signals permit
verification of the DVB specification which is referenced to the Viterbi decoder output.
ACS Array
Trace-back
RAM
Traceback Memory
Controller
Decoder
Quality
Estimate
Last-In
First-Out
Buffer
Data
Out
Viterbi
Lock
Clock
Out
Depuncturing
Logic
Branch Metric
Calculator
Change Puncture Phase
Change Carrier Phase
I
Q
G1
G2
3
3
128
F
IGURE
18: V
ITERBI
D
ECODER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDM8515 | ANALOG IC - DATASHEET REFERENCE |
| HDM8515P | Operational Amplifier (Op-Amp) IC; Number of Amplifiers:4; Package/Case:14-DIP; Op Amp Type:Low Power; Single Supply Voltage Min (+V):3V; Dual Supply Voltage Max (+/- V):16V; Amplifier Type:Operational; Mounting Type:Through Hole |
| HE6SF200 | High efficiency super fast silicon rectifier diode |
| HE82005 | 8-BIT MICRO-CONTROLLER |
| HE82006 | 8-BIT MICRO-CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDM8515 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:DVB/DSS Compliant Receiver |
| HDM8515P | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:DVB/DSS Compliant Receiver |
| HDM9010 | 制造商:SHOULDER 制造商全稱(chēng):SHOULDER 功能描述:Frequency Synthesizer |
| HDM9020 | 制造商:SHOULDER 制造商全稱(chēng):SHOULDER 功能描述:Frequency Synthesizer |
| HDM9030 | 制造商:SHOULDER 制造商全稱(chēng):SHOULDER 功能描述:Frequency Synthesizer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。