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參數(shù)資料
| 型號： | HDM8513AP |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | Timer IC; Supply Voltage Max:16V; Package/Case:14-DIP; Current Rating:10A; Timer Type:Timer-Dual; Mounting Type:Through Hole |
| 中文描述： | 的DVB /決策支持系統(tǒng)兼容接收器 |
| 文件頁數(shù)： | 29/67頁 |
| 文件大?。?/td> | 261K |
| 代理商： | HDM8513AP |
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29
3.7 Clock Generation PLL
An integrated VCO is locked to MxN times a reference frequency provided by a external clock.
int_clk
ext_clk
1/M
1/2
1
0
1/N
enable
PLL Analog Core
F
Ref
F
Fb
Reference
Divider
Feedback
Divider
F
IGURE
20: C
LOCK
S
IGNAL
G
ENERATION
This programmable PLL consists of a PLL analog core, a reference divider with a divider ratio M, a
feedback divider with a divider ratio N, and a divider which askes the duty cycle 1/2.
Reference divider and feedback divider are used to synthesize various frequencies from a reference
frequency,
Since PLL synchronizes the frequency and phase of two signals, F
Ref
and F
Fb
,
Internal clock is calculated as follows
The following two PLL modes are provided to control PLL.
(1) PLL Enable mode : The internal clock is connected to the generated clock of the PLL.
(2) PLL Disable mode : The PLL is bypassed and the external clock is directly connected to the
internal clock.
More information can be found on the part of the write register.
f
ext_clk
M
=
f
int_clk
N
f
int_clk
=
M
N
f
ext_clk
f
ext_clk.
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