參數(shù)資料
型號： HDM8513A
廠商： Hynix Semiconductor Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Linear Voltage Regulator IC; Package/Case:3-TO-92; Supply Voltage:30V; Output Voltage:5V; Current Rating:0.1A; Operating Temp. Max:70 C; Operating Temp. Min:0 C; Output Voltage Max:5V; Voltage Regulator Type:Positive Voltage
中文描述： 的DVB /決策支持系統(tǒng)兼容接收器
文件頁數(shù)： 5/67頁
文件大?。?/td> 261K
代理商： HDM8513A
F
IGURE
7: M
OTOROLA
R
EAD
T
IMING
D
IAGRAM
....................................................................................................14
F
IGURE
8: M
OTOROLA
W
RITE
T
IMING
D
IAGRAM
.................................................................................................15
F
IGURE
9: O
UTPUT
T
IMING
D
IAGRAM FOR
N
ORMAL
P
ARALLEL
.......................................................................16
F
IGURE
10: O
UTPUT
T
IMING
D
IAGRAM FOR
N
ORMAL
S
ERIAL
...........................................................................16
F
IGURE
11: O
UTPUT
T
IMING
D
IAGRAM FOR
R
EGULATED
P
ARALLEL
...............................................................17
F
IGURE
12: O
UTPUT
T
IMING
D
IAGRAM FOR
R
EGULATED
S
ERIAL MODE
1.......................................................17
F
IGURE
13: O
UTPUT
T
IMING
D
IAGRAM FOR
R
EGULATED
S
ERIAL MODE
2.......................................................17
F
IGURE
14: ADC B
LOCK
D
IAGRAM
............................................................................................................................ 19
F
IGURE
15: D
EMODULATOR
B
LOCK
D
IAGRAM
.......................................................................................................20
F
IGURE
16: N
OISE
M
EASUREMENT
C
IRCUIT
...........................................................................................................22
F
IGURE
17: N
OISE
A
CCUMULATOR AS A FUNCTION OF
SNR
AND
T
IME
............................................................ 23
F
IGURE
18: V
ITERBI
D
ECODER
...................................................................................................................................24
F
IGURE
19: R
EED
S
OLOMON
D
ECODER
....................................................................................................................28
F
IGURE
20: C
LOCK
S
IGNAL
G
ENERATION
................................................................................................................29
F
IGURE
21: T
YPICAL
S
ET
T
OP
B
OX
D
EMODULATOR
............................................................................................ 30
F
IGURE
22: M
ECHANICAL
C
ONFIGURATION
...........................................................................................................32
F
IGURE
23: M
ECHANICAL
C
ONFIGURATION
...........................................................................................................34
F
IGURE
24: A
NALOG
P
IN
C
ONNECTION
....................................................................................................................35
F
IGURE
25: CLOCK GENERATION CIRCUIT
..........................................................................................................35
F
IGURE
26: I2C W
RITE TO THE
HDM8513A...........................................................................................................40
F
IGURE
27: I2C R
EAD FROM THE
HDM8513A.........................................................................................................41
F
IGURE
A1: S
YMBOL
T
IMING
R
ECOVERY
T
RANSIENT
R
ESPONSE
.......................................................................59
F
IGURE
A2: C
ARRIER
P
HASE
R
ECOVERY
T
RANSIENT
R
ESPONSE
........................................................................60
F
IGURE
A3: C
ARRIER
P
HASE
R
ECOVERY
T
RANSIENT
R
ESPONSE WITH
L
OW
SNR..........................................61
F
IGURE
A4: A
DJACENT
C
HANNEL
I
NTERFERENCE OF
10
D
B, 1.35 S
PACING
....................................................64
F
IGURE
A5: P
ERFORMANCE WITH INTERFERER AT DIFFERENT CARRIER SPACINGS
.....................................65
F
IGURE
A6: P
ERFORMANCE WITH
+10
D
B I
NTERFERER
......................................................................................66
LIST OF TABLES
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
...............................................................................................................8
T
ABLE
2: DC C
HARACTERISTICS
.................................................................................................................................8
T
ABLE
3: D
EMODULATOR
S
PECIFICATIONS
.............................................................................................................9
T
ABLE
4: AC C
HARACTERISTICS
.................................................................................................................................9
T
ABLE
5: I
NTEL
80C88A R
EAD
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
= 1)................................................10
T
ABLE
6: I
NTEL
80C88A W
RITE
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
= 1).............................................11
T
ABLE
7: I
NTEL
8051 R
EAD
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
= 1)......................................................12
T
ABLE
8: I
NTEL
8051 W
RITE
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
= 1)...................................................13
T
ABLE
9: M
OTOROLA
R
EAD
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
=0)....................................................14
T
ABLE
10:
M
OTOROLA
W
RITE
C
YCLE
T
IMING
P
ARAMETERS
(B
USMODE
=0).................................................15
T
ABLE
11: O
UTPUT
T
IMING
.......................................................................................................................................16
T
ABLE
12: E
XAMPLE OF
A
CQUISITION
T
IMING
.....................................................................................................26
T
ABLE
13: I2C S
LAVE
A
DDRESS
..................................................................................................................................41
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