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4
TABLE OF CONTENTS
1. INTRODUCTION TO THE HDM8513A................................................................................................................6
1.1 F
EATURES AND
B
ENEFITS
..................................................................................................................................7
2. HARDWARE SPECIFICATION..............................................................................................................................8
3. TECHNICAL OVERVIEW.....................................................................................................................................18
3.1 D
UAL
C
HANNEL
A
NALOG TO
D
IGITAL
C
ONVERTER
..................................................................................18
3.2 V
ARIABLE
R
ATE
D
EMODULATOR
..................................................................................................................20
3.3 N
OISE
M
EASUREMENT
C
IRCUIT
.....................................................................................................................22
3.4 V
ITERBI
D
ECODER
.............................................................................................................................................24
3.5 A
UTONOMOUS
A
CQUISITION
..........................................................................................................................25
3.6 R
EED
S
OLOMON
D
ECODER
..............................................................................................................................27
3.7 C
LOCK
G
ENERATION
PLL.................................................................................................................................29
3.8 DBS R
ECEIVER
...................................................................................................................................................30
4. MECHANICAL SPECIFICATIONS.....................................................................................................................31
4.1 100 P
IN
Q
UAD
F
LAT
P
ACK
................................................................................................................................31
4.2 64 P
IN
T
HIN
Q
UAD
F
LAT
P
ACK
........................................................................................................................33
4.3 R
ECOMMENDED
A
NALOG
P
IN
C
ONNECTION
...............................................................................................35
4.4 R
ECOMMENDED
C
LOCK
G
ENERATION
C
IRCUIT
...........................................................................................35
5. SIGNAL DESCRIPTION....................................................................................................................................... 36
5.1 I
NPUTS
..................................................................................................................................................................36
5.2 O
UTPUTS
.............................................................................................................................................................36
5.3 M
ONITOR AND
C
ONTROL
I
NTERFACE
...........................................................................................................39
5.4 I2C M
ODE
.............................................................................................................................................................40
6. REGISTER DEFINITIONS.....................................................................................................................................42
6.1 W
RITE
R
EGISTERS
..............................................................................................................................................42
6.2 R
EAD
R
EGISTERS
................................................................................................................................................55
APPENDIX....................................................................................................................................................................58
A1. L
OOP
F
ILTER
P
ROGRAMMING
A
PPLICATION
N
OTE
................................................................................59
A2. F
ALSE
L
OCK
E
SCAPE
A
PPLICATION
N
OTE
.................................................................................................62
A3. P
ERFORMANCE WITH
I
NTERFERENCE
..........................................................................................................63
A4. N
YQUIST
C
RITERIA
C
ONSIDERATIONS
.........................................................................................................67
LIST OF FIGURES
F
IGURE
1: T
OP
L
EVEL
B
LOCK
D
IAGRAM
....................................................................................................................6
F
IGURE
2: I
NPUT
D
ATA
T
IMING
D
IAGRAM
...............................................................................................................9
F
IGURE
3: I
NTEL
80C88A R
EAD
T
IMING
D
IAGRAM
...............................................................................................10
F
IGURE
4: I
NTEL
80C88A W
RITE
T
IMING
D
IAGRAM
.............................................................................................11
F
IGURE
5: I
NTEL
8051 R
EAD
T
IMING
D
IAGRAM
.....................................................................................................12
F
IGURE
6: I
NTEL
8051 W
RITE
T
IMING
D
IAGRAM
...................................................................................................13