
List of Items Revised or Added for This Version
Section
Page
Item
Description
1.1 Overview
3
Table 1.1 Features
Description of time
specification amended
2.8.1 Memory Map
46
Figure 2.16(2) H8/3801 Memory
Map
Figure amended
47
Figure 2.16(3) H8/3800 Memory
Map
Figure amended
3.3.1 Overview
60
Table 3.2 Interrupt Sources and
Their Priorities
Amended
3.3.2 Interrupt Control
Registers
61
Table 3.3 Interrupt Control
Registers
Initial values amended
1. IRQ edge select register (IEGR) Bits 4 to 2 amended
62
2. Interrupt enable register 1
(IENR1)
Bits 6, 4, and 3 amended
63 to 65
3. Interrupt enable register 2
(IENR2)
Bits 5, 4, and 1 amended
65
4. Interrupt request register 1
(IRR1)
Bits 6, 4, and 3 amended
67, 68
5. Interrupt request register 2
(IRR2)
Bits 5, 4, and 1 amended
3.3.5 Interrupt
Operations
74
Figure 3.3 Flow up to Interrupt
Acceptance
Figure amended
3.4.2 Notes on
Rewriting Port Mode
Registers
79
Table 3.5 Conditions under which
Interrupt Request Flag is Set to 1
IRREC2 flag condition
amended
3.4.3 Interrupt
Request Flag Clearing
Methods
80
3.4.3 Interrupt Request Flag
Clearing Method
Description added
4.5 Note on Oscillators 90 to 92
4.5.1 Definition of Oscillation
Setting Standby Time
4.5.2 Notes on Use of Crystal
Oscillator Element(Excluding
Ceramic Oscillator Element)
Description added
5.1 Overview
95
Table 5.2 Internal State in Each
Operating Mode
Note 7 amended
5.3.3 Oscillator Setting
Time after Standby
Mode is Cleared
103
Table 5.4 Clock Frequency and
Setting Time
Changed