參數(shù)資料
型號: HCTS74T
廠商: Intersil Corporation
英文描述: Radiation Hardened Dual-D Flip-Flop with Set and Reset(抗輻射雙D觸發(fā)器(帶置位、復位))
中文描述: 雙輻射加固與設置和復位(抗輻射雙?觸發(fā)器(帶置位,復位)- D觸發(fā)器)
文件頁數(shù): 3/3頁
文件大?。?/td> 124K
代理商: HCTS74T
4-3
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
(2261
μ
m x 2235
μ
m x 533
μ
m
±
51
μ
m)
89 x 88 x 21mils
±
2mil
METALLIZATION:
Type: Al Si
Thickness: 11k
±
1k
SUBSTRATE POTENTIAL:
Unbiased (Silicon on Sapphire)
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 13k
±
2.6k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
200
PROCESS:
CMOS SOS
Metallization Mask Layout
HCTS74T
R1
(1)
V
CC
(14)
CP1 (3)
S1 (4)
Q1 (5)
Q1 (6)
(8)
Q2
(9)
Q2
(10) S2
(11) CP2
(12) D2
(13) R2
D1
(2)
NC
NC
(7)
GND
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask
series for the HCTS74 is TA14438A.
HCTS74T
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