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參數(shù)資料
| 型號： | HCTS10K |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Triple 3-Input NAND Gate |
| 中文描述： | 輻射加固三3輸入與非門 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 147K |
| 代理商： | HCTS10K |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
HCTS10MS
Radiation Hardened
Triple 3-Input NAND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUTS
An
Bn
Cn
Yn
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
L
NOTE: L = Logic Level Low, H = Logic level High
A1
B1
A2
B2
C2
Y2
GND
VCC
C1
Y1
C3
B3
A3
Y3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
A1
B1
A2
B2
C2
Y2
GND
VCC
C1
Y1
C3
B3
A3
Y3
An
Bn
Yn
(6, 8, 12)
(1, 3, 9)
(2, 4, 10)
(5, 11, 13)
Cn
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
- LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS10MS is a Radiation Hardened Triple 3-Input
NAND Gate. A high on all inputs forces the output to a Low state.
The HCTS10MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS10MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
SCREENING
LEVEL
PACKAGE
HCTS10DMSR
-55
o
C to +125
o
C
Intersil Class
S Equivalent
14 Lead SBDIP
HCTS10KMSR
-55
o
C to +125
o
C
Intersil Class
S Equivalent
14 Lead Ceramic
Flatpack
HCTS10D/
Sample
+25
o
C
Sample
14 Lead SBDIP
HCTS10K/
Sample
+25
o
C
Sample
14 Lead Ceramic
Flatpack
HCTS10HMSR
+25
o
C
Die
Die
September 1995
Spec Number
518778
File Number
2434.2
相關PDF資料 |
PDF描述 |
|---|---|
| HCTS10KMSR | Radiation Hardened Triple 3-Input NAND Gate |
| HCTS10MS | Quadruple 2-Input Exclusive-OR Gates 20-LCCC -55 to 125 |
| HCTS112D | Quadruple 2-Input Exclusive-OR Gates 14-CDIP -55 to 125 |
| HCTS112DMSR | Quadruple 2-Input Exclusive-OR Gates 14-CFP -55 to 125 |
| HCTS112K | Radiation Hardened Dual JK Flip-Flop |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HCTS10KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NAND Gate |
| HCTS10MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NAND Gate |
| HCTS112D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCTS112DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCTS112HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
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