參數(shù)資料
型號(hào): HC5515CMZ
廠商: INTERSIL CORP
元件分類: 模擬傳輸電路
英文描述: ITU CO/PABX SLIC with Low Power Standby
中文描述: TELECOM-SLIC, PQCC28
封裝: ROHS COMPLIANT, PLASTIC, MS-018AB, LCC-28
文件頁數(shù): 16/20頁
文件大?。?/td> 469K
代理商: HC5515CMZ
16
FN4235.6
June 6, 2006
3.4kHz and compare to 1kHz reading.
V
TR
and E
RX
are defined in Figure 9.
18. Four-Wire to Four-Wire Frequency Response -
The 4-wire
to 4-wire frequency response is measured with respect to
E
RX
= 0dBm at 1.0kHz, E
G
= 0V, I
DCMET
= 23mA. The
frequency response is computed using the following equation:
F
4-4
= 20
log (V
TX
/E
RX
), vary frequency from 300Hz to
3.4kHz and compare to 1kHz reading.
V
TX
and E
RX
are defined in Figure 9.
19. Two-Wire to Four-Wire Insertion Loss -
The 2-wire to 4-wire
insertion loss is measured with respect to E
G
= 0dBm at 1.0kHz
input signal, E
RX
= 0, I
DCMET
= 23mA and is computed using
the following equation:
L
2-4
= 20
log (V
TX
/V
TR
)
where: V
TX
, V
TR
, and E
G
are defined in Figure 9. (Note: The
fuse resistors, R
F
, impact the insertion loss. The specified
insertion loss is for R
F
= 0).
20. Four-Wire to Two-Wire Insertion Loss -
The 4-wire to 2-wire
insertion loss is measured based upon E
RX
= 0dBm, 1.0kHz
input signal, E
G
= 0, I
DCMET
= 23mA and is computed using
the following equation:
L
4-2
= 20
log (V
TR
/E
RX
),
where: V
TR
and E
RX
are defined in Figure 9.
21. Two-Wire to Four-Wire Gain Tracking -
The 2-wire to 4-wire
gain tracking is referenced to measurements taken for
E
G
= -10dBm, 1.0kHz signal, E
RX
= 0, I
DCMET
= 23mA and is
computed using the following equation.
G
2-4
= 20
log (V
TX
/V
TR
) vary amplitude -40dBm to +3dBm, or
-55dBm to -40dBm and compare to -10dBm reading.
V
TX
and V
TR
are defined in Figure 9.
22. Four-Wire to Two-Wire Gain Tracking -
The 4-wire to 2-wire
gain tracking is referenced to measurements taken for
E
RX
= -10dBm, 1.0kHz signal, E
G
= 0, I
DCMET
= 23mA and is
computed using the following equation:
G
4-2
= 20
log (V
TR
/E
RX
) vary amplitude -40dBm to +3dBm, or
-55dBm to -40dBm and compare to -10dBm reading.
V
TR
and E
RX
are defined in Figure 9. The level is specified at
the 4-wire receive port and referenced to a 600
impedance
level.
23. Two-Wire Idle Channel Noise -
The 2-wire idle channel noise
at V
TR
is specified with the 2-wire port terminated in 600
(R
L
)
and with the 4-wire receive port grounded (Reference Figure 10).
24. Four-Wire Idle Channel Noise -
The 4-wire idle channel noise
at V
TX
is specified with the 2-wire port terminated in 600
(R
L
).
The noise specification is with respect to a 600
impedance
level at V
TX
. The 4-wire receive port is grounded (Reference
Figure 10).
25. Harmonic Distortion (2-Wire to 4-Wire) -
The
distortion is measured with the following conditions.
E
G
= 0dBm at 1kHz, I
DCMET
= 23mA. Measurement taken at
V
TX
. (Reference Figure 7).
harmonic
26. Harmonic Distortion (4-Wire to 2-Wire) -
The
distortion is measured with the following conditions. E
RX
=
0dBm0. Vary frequency between 300Hz and 3.4kHz, I
DCMET
=
23mA. Measurement taken at V
TR
. (Reference Figure 9).
harmonic
27. Constant Loop Current -
The
calculated using the following equation:
constant
loop
current
is
I
L
= 2500 / (R
DC1
+ R
DC2
).
28. Standby State Loop Current -
The standby state loop current
is calculated using the following equation:
I
L
= [|V
BAT
| - 3] / [R
L
+1800], T
A
= 25°C.
29. Power Supply Rejection Ratio -
Inject a 100mV
RMS
signal
(50Hz to 4kHz) on V
BAT
, V
CC
and V
EE
supplies. PSRR is
computed using the following equation:
PSRR = 20
log (V
TX
/V
IN
). V
TX
and V
IN
are defined in Figure 11.
Pin Descriptions
PLCC
SYMBOL
DESCRIPTION
1
RING
SENSE
Internally connected to output of RING power amplifier.
2
BGND
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
4
V
CC
+5V power supply.
5
RINGRLY
Ring relay driver output.
6
V
BAT
Battery supply voltage, -24V to -56V.
7
R
SG
Saturation guard programming resistor pin.
8
NC
This pin is used during manufacturing. This pin is to be left open for proper SLIC operation.
9
E0
TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set to
a logic level one.
11
DET
Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered (see
Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET output is
an open collector with an internal pull-up of approximately 15k
to V
CC.
12
C2
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
or Standby) of the SLIC.
HC5515
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