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參數(shù)資料
| 型號： | GS841E18AT-166I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 256K x 18 Sync Cache Tag |
| 中文描述： | 256K X 18 CACHE TAG SRAM, 8.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 421K |
| 代理商： | GS841E18AT-166I |
GS841E18AT/B-180/166/150/130/100
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 4/2005
8/21
2001, GSI Technology
Notes:
1.
X means “don’t care,” H means “l(fā)ogic high,” L means “l(fā)ogic low.”
2.
3.
4.
5.
6.
Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
All inputs, except OE, must meet setup and hold on rising edge of CLK.
Suspending busrt generates a wait cycle.
ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).
A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle.
Refer to
page 12
for the Write timing diagram.
Synchronous Truth Table
Operation
Address Used
CE1
CE2
CE3
ADSP
ADSC
ADV
Write
OE
CLK
DQ
Deselect Cycle, Power Down
none
H
X
X
X
L
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
L
X
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
X
H
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
L
X
H
L
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
X
H
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
external
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
external
L
H
L
L
X
X
X
H
L-H
High-Z
Read Cycle, Begin Burst
external
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
external
L
H
L
H
L
X
H
H
L-H
High-Z
Write Cycle, Begin Burst
external
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Continue Burst
next
X
X
X
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
next
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
next
H
X
X
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
next
H
X
X
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
next
X
X
X
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
next
H
X
X
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
current
X
X
X
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
current
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
current
H
X
X
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
current
H
X
X
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
current
X
X
X
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
current
H
X
X
X
H
H
L
X
L-H
D
相關(guān)PDF資料 |
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|---|---|
| GS841E18AT-180 | 256K x 18 Sync Cache Tag |
| GS841E18AT-180I | 256K x 18 Sync Cache Tag |
| GS841Z18AGT-100 | 4Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS841Z18AGT-100I | 4Mb Pipelined and Flow Through Synchronous NBT SRAMs |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| GS841E18AT-180 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS841E18AT-180I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS841Z18AGT-100 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS841Z18AGT-100I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS841Z18AGT-150 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs |
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