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參數(shù)資料
| 型號： | GS8170LW36AC |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 18Mb ヒ1x1Lp CMOS I/O Late Write SigmaRAM |
| 中文描述： | 35.7ヒ1x1Lp的CMOS的I / O后寫入SigmaRAM |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 765K |
| 代理商： | GS8170LW36AC |
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GS8170LW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
9/32
2003, GSI Technology
SigmaRAM Late Write SRAM Burst Writes with Counter Wrap-around
Burst Order
The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have
been accessed. SigmaRAMs always count in linear burst order.
Note:
The burst counter wraps to initial state on the 5th rising edge of clock.
Echo Clock
SRAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
Linear Burst Order
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
D1
D2
XX
XX
A2
Counter Wraps
CQ
Continue
/E
1
ADV
DQ
D2
ADV
Continue
CK
Address
A2
XX
XX
XX
Continue
Continue
Write
D0
/W
A1
A2
A3
A0
D3
Internal
Address
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