參數(shù)資料
型號(hào): GS8161FZ18BD-5.5
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 18Mb Flow Through Synchronous NBT SRAM
中文描述: 1M X 18 ZBT SRAM, 5.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 16/28頁(yè)
文件大?。?/td> 629K
代理商: GS8161FZ18BD-5.5
GS8161FZ18/32/36BD
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 6/2006
16/28
2006, GSI Technology
Operating Currents
Parameter
Test Conditions
Mode
Symbol
-5.5
-6.5
-7.5
Unit
0
to
70°C
40
to
85°C
0
to
70°C
40
to
85°C
0
to
70°C
40
to
85°C
Operating
Current
Device Selected;
All other inputs
V
IH
o
r
V
IL
Output
open
(x32/
x36)
Flow Through
I
DD
I
DDQ
235
20
245
20
205
15
215
15
190
15
200
15
mA
(x18)
Flow Through
I
DD
I
DDQ
215
10
225
10
190
10
200
10
175
10
185
10
mA
Standby
Current
ZZ
V
DD
– 0.2 V
Flow Through
I
SB
40
50
40
50
40
50
mA
Deselect
Current
Device Deselected;
All other inputs
V
IH
or
V
IL
Flow Through
I
DD
60
65
50
55
50
55
mA
Notes:
1.
2.
I
DD
and I
DDQ
apply to any combination of V
DD3
, V
DD2
, V
DDQ3
, and V
DDQ2
operation.
All parameters listed are worst case scenario.
AC Electrical Characteristics
Parameter
Symbol
-5.5
-6.5
-7.5
Unit
Min
Max
Min
Max
Min
Max
Flow Through
Clock Cycle Time
tKC
5.5
6.5
7.5
ns
Clock to Output Valid
tKQ
5.5
6.5
7.5
ns
Clock to Output Invalid
tKQX
2.0
2.0
2.0
ns
Clock to Output in Low-Z
tLZ
1
2.0
2.0
2.0
ns
Setup time
tS
1.5
1.5
1.5
ns
Hold time
tH
0.5
0.5
0.5
ns
Clock HIGH Time
tKH
1.3
1.3
1.5
ns
Clock LOW Time
tKL
1.5
1.5
1.7
ns
Clock to Output in
High-Z
tHZ
1
1.5
2.5
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
2.5
3.0
3.8
ns
G to output in Low-Z
tOLZ
1
0
0
0
ns
G to output in High-Z
tOHZ
1
2.5
3.0
3.8
ns
ZZ setup time
tZZS
2
5
5
5
ns
ZZ hold time
tZZH
2
1
1
1
ns
ZZ recovery
tZZR
20
20
20
ns
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
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GS8161FZ18BD-5.5I 18Mb Flow Through Synchronous NBT SRAM
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