參數(shù)資料
型號: GMM7738280CTG-5
英文描述: x72 EDO Page Mode DRAM Module
中文描述: x72 EDO公司頁面模式內存模塊
文件頁數(shù): 5/27頁
文件大?。?/td> 401K
代理商: GMM7738280CTG-5
LG Semicon
GMM77316380CTG-5/6
5
Capacitance
(V
CC
= 3.3V+/-0.3V, T
A
= 25C, f = 1MHz)
Symbol
C
I1
Parameter
Note
1
Unit
pF
Max
20
Min
-
C
I2
C
13
C
14
Input Capacitance (A0~A12,B0)
Input Capacitance (WE0, WE2, OE0, OE2)
Input Capacitance (RAS0,RAS2)
Input Capacitance (CAS0,CAS4)
1, 2
1, 2
1, 2
pF
pF
pF
20
65
20
-
-
-
C
I/O
I/O Capacitance (DQ0~DQ71)
1, 2
pF
20
-
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = V
IH
to disable D
OUT
.
AC Characteristics
(V
CC
= 3.3V+/-0.3V, T
A
= 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns Output timing reference levels : V
OL
/V
OH
= 0.8/2.0V
Input level : V
IL
/V
IH
= 0.0/3.0V Output load : 1 TTL gate+C
L
(100pF)
Input timing reference levels : V
IL
/V
IH
= 0.8/2.0V (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Max
Max
Min
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
4
t
RAD
3
t
RSH
t
CSH
t
CRP
Min
84
30
50
8
5
8
0
8
12
10
18
35
10
-
-
10000
-
-
-
-
32
20
-
-
-
Unit Notes
§ à
§ à
§ à
§ à
§ à
§ à
§ à
§ à
§ à
§ à
§ à
§ à
§ à
t
T
t
REF
Refresh Period ( 8192 Cycles)
2
-
50
64
§ à
ms
t
ODD
t
DZO
t
DZC
18
0
0
-
-
-
§ à
§ à
§ à
60
10
104
-
40
-
10000
5
-
10
-
0
-
10
-
14
40
12
25
20
-
40
-
10
-
20
-
0
-
0
-
2
50
-
64
t
CP
8
-
§ à
10
-
10000
10000
GMM77316380CTG-5 GMM77316380CTG-6
Parameter
Random Read or Write Cycle Time
RAS Precharge Time
RAS Pulse Width
CAS Pulse Width
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
TransitionTime
(Rise and Fall)
OE to D
IN
Delay Time
OE Delay Time from D
IN
CAS Set-up Time from D
IN
CAS Precharge Time
5
6
6
7
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