參數(shù)資料
型號(hào): LTC2223IUK#PBF
廠商: Linear Technology
文件頁數(shù): 15/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 80MSPS SAMPLE 48QFN
標(biāo)準(zhǔn)包裝: 52
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 406mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)單端,雙極; 1 個(gè)差分,雙極
產(chǎn)品目錄頁面: 1349 (CN2011-ZH PDF)
LTC2222/LTC2223
22
22223fb
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Figure 13. Digital Output Buffer
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single out-
put buffer. Each buffer is powered by OVDD and OGND,
isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the digi-
tal output loading can affect the performance. The digital
outputs of the LTC2222/LTC2223 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
The lower limit of the LTC2222/LTC2223 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specied minimum operating
frequency for the LTC2222/LTC2223 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11 – D0
(OFFSET BINARY)
D11 – D0
(2’s COMPLEMENT)
>+1.000000V
+0.999512V
+0.999024V
1
0
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
1
0000 0000 0001
0000 0000 0000
1000 0000 0001
1000 0000 0000
22223 F12a
ENC
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1μF
LTC2222/
LTC2223
22223 F12b
ENC
ENC+
130Ω
3.3V
130Ω
D0
Q0
MC100LVELT22
LTC2222/
LTC2223
83Ω
LTC2222/LTC2223
22223 F13
OVDD
VDD
0.1μF
43Ω
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
APPLICATIONS INFORMATION
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