參數(shù)資料
型號(hào)： ES1371
廠商： Electronic Theatre Controls, Inc.
英文描述： ENSONIQ AudioPCI 97 digital controller
中文描述： ENSONIQ AudioPCI 97數(shù)字控制器
文件頁(yè)數(shù)： 25/37頁(yè)
文件大?。?/td> 103K
代理商： ES1371
ENSONIQ Proprietary Information
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
25
in pause mode the channel will playback the last sample.
0 - Play mode ; normal playback mode or removes channel
from pause mode on next sample after bit is
cleared
1 - Pause mode ; plays last sample continuously on next sample
after the pause bit has been set
This bit is the interrupt enable bit for the ADC channel. To clear the
interrupt this bit must be set to zero and then set to one to enable the
next interrupt.
0 - ADC interrupt disabled
1 - ADC interrupt enabled
This bit is the interrupt enable bit for the DAC2 channel. To clear
the interrupt this bit must be set to zero and then set to one to enable
the next interrupt.
0 - DAC2 interrupt disabled
1 - DAC2 interrupt enabled
This bit is the interrupt enable bit for the DAC1 channel. To clear
the interrupt this bit must be set to zero and then set to one to enable
the next interrupt.
0 - DAC1 interrupt disabled
1 - DAC1 interrupt enabled
This bit when set high will force the sample counter for DAC1 to be
reloaded with the sample count register value on the next rising
edge of the DAC1 left/right clock. This bit can be returned low on
the following instruction. It does not have to be held high for more
than 1 microsecond. This control bit is rising edge triggered.
This bit when set high will enable the DAC2 to continue playback
when it is in the stopped condition and the DAC2 channel has been
disabled. Without this bit set if the DAC2 channel is disabled it will
begin to playback zeros.
0 - DAC2 plays back zeros when disabled
1 - DAC2 plays back last sample when disabled and in stop mode
These two bits select the data format for the ADC channel. For eight
bit data modes the msb is always inverted before it is written out to
the buffer. For mono modes only the left channel data is recorded.
00 - Eight bit - Mono mode
01 - Eight bit - Stereo mode
10 - Sixteen bit - Mono mode
11 - Sixteen bit - Stereo mode
These two bits select the data format for the DAC2 channel. For
eight bit data modes the msb is always inverted after it is read from
the buffer. For mono modes the left channel data is duplicated for
both the left and right channels.
00 - Eight bit - Mono mode
01 - Eight bit - Stereo mode
10 - Sixteen bit - Mono mode
11 - Sixteen bit - Stereo mode
These two bits select the data format for the DAC1 channel. For
eight bit data modes the msb is always inverted after it is read from
the buffer. For mono modes the left channel data is duplicated for
both the left and right channels.
00 - Eight bit - Mono mode
01 - Eight bit - Stereo mode
10 - Sixteen bit - Mono mode
10
R/W
R1_INT_EN
9
R/W
P2_INTR_EN
8
R/W
P1_INTR_EN
7
R/W
P1_SCT_RLD
6
R/W
P2_DAC_SEN
5:4
R/W
R1_S_EB :
R1_S_MB
3:2
R/W
P2_S_EB :
P2_S_MB
1:0
R/W
P1_S_EB :
P1_S_MB
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