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ENSONIQ Proprietary Information
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
19
UART Control Register
Addressable as byte only
Power on reset value 00H
Bit(s)
R/W
15
W
Address 09H
Direct Mapped
Name
RXINTEN
Function
This bit is the UART receiver interrupt enable bit.
0 - UART receiver interrupts disabled
1 - UART receiver interrupts enabled
These two bits are the control bits for the UART transmitter
operation.
00 -
01 - Txrdy interrupts enabled
10 -
11 -
These bits are undefined
These two bits are the control bits for the UART.
00 -
01 -
10 -
11 - Software Reset
14:13
W
TXINTEN[1:0]
12:10
9:8
UNDEFINED
CNTRL[1:0]
W
UART Reserved Register
Addressable as byte only
Power on reset value 00H
Bit(s)
R/W
7:1
0
R/W
Address 0AH
Direct Mapped
Name
UNDEFINED
TEST_MODE
Function
These bits are undefined.
This bit enables the UART test mode. When the test mode bit is set
the UART clock is switched to the PCI bus clock. The faster clock
reduces the size of the test vectors and also shortens the run time of
the test vectors. The power up state is normal mode enabled.
0 - Normal mode enabled.
1 - UART test mode enabled.
7.3.
Host Interface - Memory Page
The memory page register is a four bit register used to access one of 16 memory pages within the
AUDIOPCI chip. This register can be read or written but any unused bits are undefined on read back.
Memory Page Register
Addressable as byte, word, longword
Power on reset value 0H
Bit(s)
R/W
Name
31:4
UNDEFINED
3:0
R/W
MEMORY PAGE
Address 0CH
Direct Mapped
Function
These bits are undefined.
These bits select what memory page will be accessed. Each memory
page is 16 bytes and is addressed from 30H - 3FH.