參數(shù)資料
型號(hào)： LT1366CS8#TR
廠商： Linear Technology
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP DUAL R-R I/O 8SOIC
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 通用
電路數(shù)： 2
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 0.13 V/µs
增益帶寬積： 400kHz
電流 - 輸入偏壓： 10nA
電壓 - 輸入偏移： 200µV
電流 - 電源： 370µA
電流 - 輸出 / 通道： 75mA
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 30 V，±0.9 V ~ 15 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
LT1366/LT1367
LT1368/LT1369
1366fb
Technology’sproprietarycomplementarybipolarprocess,
which ensures very similar DC and AC characteristics for
the output devices Q24 and Q26.
AsimplecomparatorQ5steerscurrentfromcurrentsource
I1 between the two input stages. When the input common
mode voltage VCM is near the negative supply, Q5 is re-
verse biased, and I1 becomes the tail current for the PNP
differential pair Q1/Q2. At the other extreme, when VCM
is within about 1.3V from the positive supply, Q5 diverts
I1 to the current mirror D3/Q6, which furnishes the tail
current for the NPN differential pair Q3/Q4.
The collector currents of the two input pairs are combined
in the second stage, consisting of Q7 through Q11. Most
of the voltage gain in the amplifier is contained in this
stage. Differential amplifier Q14/Q15 buffers the output
of the second stage, converting the output voltage to dif-
ferential currents. The differential currents pass through
current mirrors D4/Q17 and D5/Q16, and are converted to
differential voltages by Q18 and Q19. These voltages are
also buffered and applied to the output Darlington pairs
Q23/Q24 and Q25/Q26. Capacitors C1 and C2 form local
feedback loops around the output devices, lowering the
output impedance at high frequencies.
Input Offset Voltage
Since the amplifier has two input stages, the input offset
voltage changes depending upon which stage is active.
Theinputoffsetsarerandom,butboundedvoltages.When
the amplifier switches between stages, offset voltages
may go up, down, or remain flat; but will not exceed the
guaranteed limits. This behavior is illustrated in three
distribution plots of input offset voltage in the Typical
Performance Characteristics section.
Overdrive Protection
Two circuits prevent the output from reversing polarity
when the input voltage exceeds the common mode range.
When the noninverting input exceeds the positive supply
by approximately 300mV, the clamp transistor Q12 (Fig-
ure 1) turns on, pulling the output of the second stage
low, which forces the output high. For inputs below the
negative supply, diodes D1 and D2 turn on, overcoming
the saturation of the input pair Q1/Q2.
When overdriven, the amplifier draws input current that
exceeds the normal input bias current. Figures 2 and 3
show some typical overdrive currents as a function of
input voltage. The input current must be less than 1mA of
positive overdrive or less than 7mA of negative overdrive,
for the phase reversal protection to work properly. When
the amplifier is severely overdriven, an external resistor
should be used to limit the overdrive current. In addition
to overdrive protection, the amplifier is protected against
ESD strokes up to 4kV on all pins.
applicaTions inForMaTion
COMMON MODE VOLTAGE RELATIVE TO
POSITIVE SUPPLY (mV)
–500
0
INPUT
BIAS
CURRENT
(nA)
20
40
60
80
–300
–100 VS
LT1366 F02
100
110
90
70
50
30
10
300
500
T = –55°C
T = 25°C
T = 85°C
T = 70°C
MEASURED AS A
FOLLOWER
–
+
Figure 2. Input Bias Current vs Common Mode Voltage
COMMON MODE VOLTAGE RELATIVE TO
NEGATIVE SUPPLY (mV)
–800
–110
INPUT
BIAS
CURRENT
(nA)
–90
–70
–50
–30
–600
–400
LT1366 F03
–200
–10
0
–20
–40
–60
–80
–100
VS
200
T = –55°C T = 25°C
T = 85°C
–
+
T = 70°C
MEASURED AS A FOLLOWER
Figure 3. Input Bias Current vs Common Mode Voltage
相關(guān)PDF資料
PDF描述
TSW-138-14-G-D CONN HEADER 76POS .100" DL GOLD
LT1352IN8#PBF IC OP AMP DUAL HI SPD 3MHZ 8-DIP
TLW-132-06-G-S CONN HEADER .100" 32POS SGL GOLD
LT1464ACS8#PBF IC OP-AMP JFET INPUT DUAL 8-SOIC
TSW-138-08-G-D CONN HEADER 76POS .100" DL GOLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K10ATC100-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K10ATC100-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K10ATC100-3 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K10ATC100-3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 72 LABs 66 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K10ATC144-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 72 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*