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參數(shù)資料
| 型號： | EPC16QC100 |
| 廠商： | Altera Corporation |
| 英文描述： | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| 中文描述： | 2。增強(qiáng)型配置器件（EPC4，EPC8 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 421K |
| 代理商： | EPC16QC100 |
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2–8
Configuration Handbook, Volume 2
Altera Corporation
August 2005
Functional Description
Figure 2–2. FPP Configuration
Notes to
Figure 2–2
:
(1)
The V
CC
should be connected to the same supply voltage as the configuration device.
(2)
The
nINIT_CONF
pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the
nINIT_CONF
/
nCONFIG
line. The
nINIT_CONF
pin does not need to be connected if its functionality is not used. If
nINIT_CONF
is not used,
nCONFIG
must be pulled to V
CC
either directly or through a resistor.
(3)
The enhanced configuration devices’
OE
and
nCS
pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus
II software. To turn off the internal pull-up resistors, check the
Disable nCS and
OE pull-ups on configuration device
option when generating programming files.
(4)
For
PORSEL
,
PGM[]
, and
EXCLK
pin connections, refer to
Table 2–9
.
(5)
In the 100-pin PQFP package, you must externally connect the following pins:
C-A0
to
F-A0
,
C-A1
to
F-A1
,
C-A15
to
F-A15
,
C-A16
to
F-A16
, and
BYTE#
to V
CC
. Additionally, you must make the following pin connections in both
100-pin PQFP and 88-pin Ultra FineLine BGA packages:
C-RP#
to
F-RP#
,
C-WE#
to
F-WE#
,
TM1
to V
CC
,
TM0
to
GND, and
WP#
to V
CC
.
(6)
Connect the FPGA
MSEL[]
input pins to select the FPP configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
Multiple FPGAs can be configured using a single enhanced configuration
device in FPP mode. In this mode, multiple Stratix series and/or APEX II
FPGAs are cascaded together in a daisy chain.
Enhanced Configuration
Device
DCLK
DATA[7..0]
OE
nCS
nINIT_CONF
(2)
MSEL
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
V
CC
V
CC
GND
GND
(3)
(3)
nCE
EXCLK
Stratix Series
or
APEX II Device
WE#C
RP#C
WP#
BYTE#
(5)
TM1
PORSEL
PGM[2..0]
TMO
WE#F
RP#F
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
V
CC
N.C.
N.C.
N.C.
N.C.
N.C.
(3)
(3)
C-A0
(5)
C-A1
(5)
C-A15
(5)
C-A16
(5)
A0-F
A1-F
A15-F
A16-F
(1)
(1)
n
(6)
(1)
nCEO
N.C.
(4)
(4)
(4)
VCCW
V
CC
(1)
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| EPC16QI100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
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