參數(shù)資料
型號： EPC16QC100
廠商： Altera Corporation
英文描述： 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
中文描述： 2。增強型配置器件（EPC4，EPC8
文件頁數(shù)： 24/36頁
文件大?。?/td> 421K
代理商： EPC16QC100
2–24
Configuration Handbook, Volume 2
Altera Corporation
August 2005
Power-On Reset (POR)
Power-On Reset
(POR)
The POR circuit keeps the system in reset until power supply voltage
levels have stabilized. The POR time consists of the V
CC
ramp time and a
user programmable POR delay counter. When the supply is stable and
the POR counter expires, the POR circuit releases the
OE
pin. The POR
time can be further extended by an external device by driving the
OE
pin
low.
1
Do not execute JTAG or ISP instructions until POR is complete.
Table 2–9. JTAG Interface Pins and Other Required Controller Pins
Pin Name
Pin Type
Description
TDI
Input
This is the JTAG data input pin.
Connect this pin to V
CC
if the JTAG circuitry is not used.
TDO
Output
This is the JTAG data output pin.
Do not connect this pin if the JTAG circuitry is not used (leave floating).
TCK
Input
This is the JTAG clock pin.
Connect this pin to GND if the JTAG circuitry is not used.
TMS
Input
This is the JTAG mode select pin.
Connect this pin to V
CC
if the JTAG circuitry is not used.
PGM[2..0]
Input
These three input pins select one of the eight pages of configuration data
to configure the FPGA(s) in the system.
Connect these pins on the board to select the page specified in the
Quartus II software when generating the enhanced configuration device
POF.
PGM[2]
is the MSB. Default selection is page 0;
PGM[2..0]=000
.
These pins must not be left floating.
EXCLK
Input
Optional external clock input pin that can be used to generate the
configuration clock (
DCLK
).
When an external clock source is not used, connect this pin to a valid logic
level (high or low) to prevent a floating input buffer.
PORSEL
Input
This pin selects a 2-ms or 100-ms POR counter delay during power up.
When
PORSEL
is low, POR time is 100-ms. When
PORSEL
is high, POR
time is 2 ms.
This pin must be connected to a valid logic level.
TM0
Input
For normal operation, this test pin must be connected to GND.
TM1
Input
For normal operating, this test pin must be connected to V
CC
.
相關(guān)PDF資料
PDF描述
EPC16QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8xxx 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QC100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC16xxx 435882001
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