elecTrical characTerisTics The l denotes the specifications which a" />
參數(shù)資料
型號(hào)： LT1366CS8#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 0K
描述： IC OP-AMP R-R IN/OUT DUAL 8-SOIC
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 通用
電路數(shù)： 2
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 0.13 V/µs
增益帶寬積： 400kHz
電流 - 輸入偏壓： 10nA
電壓 - 輸入偏移： 200µV
電流 - 電源： 370µA
電流 - 輸出 / 通道： 75mA
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 30 V，±0.9 V ~ 15 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
LT1366/LT1367
LT1368/LT1369
1366fb
elecTrical characTerisTics The
l
denotes the specifications which apply over the specified
temperature range of 0°C < TA < 70°C. VS = ±15V, VCM = 0V, VO = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage (LT1366/LT1368)
VCM = VCC
VCM = VEE
l
250
850
V
Input Offset Voltage (LT1367/LT1369)
VCM = VCC
VCM = VEE
l
250
1150
1000
V
VOS
Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 4, 5)
l
200
300
525
1500
V
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 4, 5)
l
200
300
750
2300
V
VOS TC
Input Offset Voltage Drift
(Note 3)
l
2
8
V/°C
IB
Input Bias Current
VCM = VCC
VCM = VEE
l
0
–45
15
–10
45
0
nA
IB
Input Bias Current Shift
VCM = VEE to VCC
l
25
90
nA
IOS
Input Offset Current
VCM = VCC
VCM = VEE
l
2
1
15
nA
IOS
Input Offset Current Shift
VCM = VEE to VCC
l
2
15
nA
Input Bias Current Match (Channel to Channel)
VCM = VCC (Note 4)
VCM = VEE (Note 4)
l
0
2
1
15
nA
AVOL
Large-Signal Voltage Gain
VO = –14.7V to 14.7V, RL = 10k
VO = –10V to 10V, RL = 2k
l
750
500
6000
V/mV
Channel Separation
VO = –10V to 10V, RL = 2k
l
110
135
dB
CMRR
Common Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 4)
l
95
89
103
dB
Common Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 4)
l
92
86
103
dB
PSRR
Power Supply Rejection Ratio
PSRR Match (Channel to Channel)
VS = ±5V to ±15V
VS = ±5V to ±15V (Note 4)
l
80
75
105
100
dB
VOL
Output Voltage Swing Low
No Load
ISINK = 0.5mA
ISINK = 10mA
l
VEE + 0.009
VEE + 0.045
VEE + 0.300
VEE + 0.014
VEE + 0.080
VEE + 0.600
V
VOH
Output Voltage Swing High
No Load
ISOURCE = 0.5mA
ISOURCE = 10mA
l
VCC – 0.014
VCC – 0.11
VCC – 0.95
VCC – 0.005
VCC – 0.055
VCC – 0.500
V
ISC
Short-Circuit Current
(Note 2)
l
±30
mA
IS
Supply Current per Amplifier
l
415
575
A
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Applies to short circuits to ground for all split supplies and for
single supplies less than 20V. Short circuits to either supply for supplies
greater than 20V total may permanently damage the part. A heat sink may
be required to keep the junction temperature below the absolute maximum
rating when the output is shorted indefinitely.
Note 3: This parameter is not 100% tested.
Note 4: Matching parameters are the difference between amplifiers A and
D and between B and C on the LT1367/LT1369; between the two amplifiers
on the LT1366/LT1368.
Note 5: Input offset voltage match is the difference in offset voltage
between amplifiers measured at both VCM = VEE and VCM = VCC.
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EP2S130F780C4N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 6627 LABs 534 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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