參數(shù)資料
型號(hào): EP1C6T324I6ES
廠商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 氣旋的FPGA系列數(shù)據(jù)手冊(cè)
文件頁數(shù): 86/104頁
文件大小: 763K
代理商: EP1C6T324I6ES
4–16
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Figure 4–2. External Timing in Cyclone Devices
All external I/O timing parameters shown are for 3.3-V LVTTL I/O
standard with the maximum current strength and fast slew rate. For
external I/O timing using standards other than LVTTL or for different
current strengths, use the I/O standard input and output delay adders in
Tables 4–40
through
4–44
.
Table 4–29
shows the external I/O timing parameters when using global
clock networks.
PRN
CLRN
D
Q
PRN
CLRN
D
Q
PRN
CLRN
D
Q
Dedicated
Clock
Bidirectional
Pin
Output Register
Input Register
OE Register
t
XZ
t
ZX
t
INSU
t
INH
t
OUTCO
Table 4–29. Cyclone Global Clock External I/O Timing Parameters
Notes (1)
,
(2)
(Part 1 of 2)
Symbol
Parameter
Conditions
t
I
N
SU
Setup time for input or bidirectional pin using IOE input
register with global clock fed by
CLK
pin
t
I
N
H
Hold time for input or bidirectional pin using IOE input
register with global clock fed by
CLK
pin
t
OUTCO
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by
CLK
pin
C
LOAD
= 10 pF
t
I
N
SUPLL
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
t
I
N
HPLL
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
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