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參數(shù)資料
| 型號： | EP1C6T324I6ES |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 氣旋的FPGA系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 79/104頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EP1C6T324I6ES |
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Altera Corporation
January 2007
4–9
Preliminary
Timing Model
Typically, the user-mode current during device operation is lower than
the power-up current in
Table 4–17
. Altera recommends using the
Cyclone Power Calculator, available on the Altera web site, to estimate
the user-mode I
CCINT
consumption and then select power supplies or
regulators based on the higher value.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Cyclone device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The
Quartus
II software issues an informational message during the design
compilation if the timing models are preliminary.
Table 4–18
shows the
status of the Cyclone device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 4–18. Cyclone Device Timing Model Status
Device
Preliminary
Final
v
v
v
v
v
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
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