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參數(shù)資料
| 型號： | EP1C6T324I6ES |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 氣旋的FPGA系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 59/104頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EP1C6T324I6ES |
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Altera Corporation
January 2007
2–53
Preliminary
I/O Structure
and DM pins to support a DDR SDRAM or FCRAM interface. I/O bank
1 can also support a DDR SDRAM or FCRAM interface, however, the
configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3
can also support a DDR SDRAM or FCRAM interface, however, all the
JTAG pins in I/O bank 3 must operate at 2.5 V.
Figure 2–35. Cyclone I/O Banks
Notes (1)
,
(2)
Notes to
Figure 2–35
:
(1)
Figure 2–35
is a top view of the silicon die.
(2)
Figure 2–35
is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
Each I/O bank has its own
VCCIO
pins. A single device can support 1.5-V,
1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a
different standard with different I/O voltages. Each bank also has dual-
purpose
VREF
pins to support any one of the voltage-referenced
standards (e.g., SSTL-3) independently. If an I/O bank does not use
voltage-referenced standards, the V
REF
pins are available as user I/O pins.
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