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參數(shù)資料
| 型號： | EP1C6T324I6ES |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 氣旋的FPGA系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 20/104頁 |
| 文件大?。?/td> | 763K |
| 代理商： | EP1C6T324I6ES |
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2–14
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Figure 2–9. R4 Interconnect Connections
Notes to
Figure 2–9
:
(1)
C4 interconnects can drive R4 interconnects.
(2)
This pattern is repeated for every LAB in the LAB row.
The column interconnect operates similarly to the row interconnect. Each
column of LABs is served by a dedicated column interconnect, which
vertically routes signals to and from LABs, M4K memory blocks, and row
and column IOEs. These column resources include:
■
■
■
LUT chain interconnects within an LAB
Register chain interconnects within an LAB
C4 interconnects traversing a distance of four blocks in an up and
down direction
Cyclone devices include an enhanced interconnect structure within LABs
for routing LE output to LE input connections faster using LUT chain
connections and register chain connections. The LUT chain connection
allows the combinatorial output of an LE to directly drive the fast input
of the LE right below it, bypassing the local interconnect. These resources
can be used as a high-speed connection for wide fan-in functions from LE
1 to LE 10 in the same LAB. The register chain connection allows the
register output of one LE to connect directly to the register input of the
next LE in the LAB for fast shift registers. The Quartus II Compiler
automatically takes advantage of these resources to improve utilization
and performance.
Figure 2–10
shows the LUT chain and register chain
interconnects.
Primary
LAB (2)
R4 Interconnect
Driving Left
Adjacent LAB can
LAB's R4 Interconnect
C4 Column Interconnects (1)
R4 Interconnect
LAB
Neighbor
LAB
Neighbor
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PDF描述 |
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| EP1C6T324I7ES | Cyclone FPGA Family Data Sheet |
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| EP1C4T144C7ES | Cyclone FPGA Family Data Sheet |
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