參數(shù)資料
型號: EP1C6T256I8ES
廠商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 氣旋的FPGA系列數(shù)據(jù)手冊
文件頁數(shù): 33/104頁
文件大小: 763K
代理商: EP1C6T256I8ES
Altera Corporation
January 2007
2–27
Preliminary
Embedded Memory
Figure 2–19. Input/Output Clock Mode in Simple Dual-Port Mode
Notes (1)
,
(2)
Notes to
Figure 2–19
:
(1)
All registers shown except the rden register have asynchronous clear ports.
(2)
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
6
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
D
ENA
Q
w
raddress[ ]
address[ ]
Memory Block
256 ′ 16
Data In
512 ′
8
1,024 ′ 4
2,04
8
′ 2
4,096 ′ 1
Read Address
Write Address
Write Ena
b
le
Read Ena
b
le
Data O
u
t
o
u
tclken
inclken
inclock
o
u
tclock
w
ren
rden
6 LAB Ro
w
Clocks
To M
u
ltiTrack
Interconnect
D
ENA
Q
b
yteena[ ]
Byte Ena
b
le
Write
P
u
lse
Generator
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