參數(shù)資料
型號： EM78568
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-BIT MICRO-CONTROLLER for FRS
中文描述： 8位微控制器為FRS
文件頁數(shù)： 14/54頁
文件大小： 494K
代理商： EM78568
EM78568
8-bit Micro-controller for FRS
__________________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
07/28/2004 V3.5
SEG15
SEG17
SEG19
SEG14
SEG16
SEG18
07H
08H
09H
R7 (PORT7 I/O data, Data RAM bank)
PAGE0 (PORT7 I/O data register)
7
6
P77
P76
R/W
R/W
Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit PORT7(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (VOX detection output, CTCSS detection output, Data RAM bank selection bit)
7
6
5
4
-
DETO
-
-
R
Bit 0 (RAM_B0) : Data RAM bank selection bit
Each bank has address 0 ~ address 255 which is total 256 (0.25k) bytes RAM size.
Data RAM bank selection : (Total RAM = 1.0K)
RAM_B1
RAM_B0
RAM bank
0
0
Bank0
0
1
Bank1
1
0
Bank2
1
1
Bank3
Bit 1 ~ Bit 5 :
(undefined) not allowed to use
Bit 6(DETO) : CTCSS tone detection
The signal passing CTCSS sub audio LPF will be extracted CTCSS tone. Then this tone will go into the
ZC(Zero-crossing detector) and output to DETO bit. This bit reflects the CTCSS tone frequency pulse
waveform. The user can count the timing to get the CTCSS frequency. Also see IOCE PAGE1 for CTCSS
block and switch control.
Bit 7 :
(undefined) not allowed to use
R8 (PORT8 I/O data, Data RAM address)
PAGE0 (PORT8 I/O data register)
7
6
5
4
3
P87
P86
P85
P84
P83
R/W
R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (Data RAM address register)
7
6
5
4
3
RAM_A7 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 7 (RAM_A0 ~ RAM_A7) : data RAM address
The data RAM bank’s selection is from R7 PAGE1 bit0 ~ bit 1 (RAM_B0 ~ RAM_B1).
5
4
3
2
1
0
P75
R/W
P74
R/W
P73
R/W
P72
R/W
P71
R/W
P70
R/W
3
-
2
-
1
-
0
RAM_B0
R/W-0
2
1
0
P82
R/W
P81
R/W
P80
R/W
2
1
0
R/W-0
R/W-0
R/W-0
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