參數(shù)資料
型號: EDD5108ADTA-5C
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits DDR SDRAM
中文描述: 64M X 8 DDR DRAM, 0.7 ns, PDSO66
封裝: PLASTIC, TSOP2-66
文件頁數(shù): 31/48頁
文件大?。?/td> 555K
代理商: EDD5108ADTA-5C
EDD5108ADTA-5C, EDD5116ADTA-5C
Preliminary Data Sheet E539E10 (Ver. 1.0)
31
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write
command
Bank
address
Issue the BST command. tBSTW (
tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
Issue the BST command. tBSTW (
tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank independently of the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued.
Row address State
Operation
1. Same
Same
ACTIVE
2. Same
Different
3. Different
Any
ACTIVE
IDLE
out0 out1
in0
in1
in2
in3
CK
/CK
DM
DQ
Command
t1
t0
t2
t3
t4
t5
t6
t7
t8
BL = 4
CL = 3
DQS
OUTPUT
INPUT
tBSTW (
tBSTZ)
High-Z
READ
WRIT
BST
NOP
NOP
tBSTZ (= CL)
READ to WRITE Command Interval
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EDD5116ADTA-5C REC3-SR_DR/H1 Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 15V; Power: 3W; Low Cost 3W converter in DIP24 Package; 1kVDC Isolation; Regulated Output; UL Approved; Continuous Short Circuit Protection; Internal SMD design; 3 Pinout Options, 3 Case Styles.; Efficiency to 75%
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