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參數(shù)資料
| 型號(hào)： | EDD5108ADTA-5C |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR SDRAM |
| 中文描述： | 64M X 8 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大小： | 555K |
| 代理商： | EDD5108ADTA-5C |
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EDD5108ADTA-5C, EDD5116ADTA-5C
Preliminary Data Sheet E539E10 (Ver. 1.0)
19
Auto-refresh command [REF]
This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The average refresh cycle is 7.8
μ
s. The output buffer becomes High-Z after auto-
refresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can
be issued tRFC
after the last auto-refresh command.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the self-
refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power down mode entry [PDEN]
tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode
continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not
disable DLL.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied.
((tSNR =)15 cycles for tCK = 5.0 ns after [SELFX]) To issue read command, tSRD has to be satisfied to adjust
DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8
μ
s.
Power down exit [PDEX]
The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD5116ADTA-5C | REC3-SR_DR/H1 Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 15V; Power: 3W; Low Cost 3W converter in DIP24 Package; 1kVDC Isolation; Regulated Output; UL Approved; Continuous Short Circuit Protection; Internal SMD design; 3 Pinout Options, 3 Case Styles.; Efficiency to 75% |
| EDD5108AFTA-5 | 512M bits DDR SDRAM |
| EDD5108ADTA-6BL-E | 512M bits DDR SDRAM |
| EDD5108ADTA-7BL-E | 512M bits DDR SDRAM |
| EDD5108AFTA-7A-E | 512M bits DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD5108ADTA-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5108ADTA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5108ADTA-6BL | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5108ADTA-6BL-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5108ADTA-6BLI | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM WTR (Wide Temperature Range) |
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