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參數(shù)資料
| 型號： | E28F200CVT80 |
| 廠商： | Intel Corp. |
| 英文描述： | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 2兆位SmartVoltage啟動塊閃存系列 |
| 文件頁數(shù)： | 51/55頁 |
| 文件大小： | 636K |
| 代理商： | E28F200CVT80 |
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E
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristicsduring read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
3. Refer to command definition table for valid A
IN
. (Table 7)
4. Refer to command definition table for valid D
IN
. (Table 7)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)
6. For boot block program/erase, RP# should be held at V
HH
or WP# should be held at V
IH
until operation completes
successfully.
7. Time t
PHBR
is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. See Test Configuration(Figure 21), 3.6 V and 3.3
±
0.3 V Standard Test component values.
10. See Test Configuration(Figure 21), 5 V Standard Test component values.
2-MBIT SmartVoltage BOOT BLOCK FAMILY
51
SEE NEW DESIGN RECOMMENDATIONS
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