參數(shù)資料
型號： DSD1608PAHR
英文描述： 8-CHANNEL, ENHANCED MULTIFORMAT, DELTA-SIGMA, DIGITAL-TO-ANALOG CONVERTER
中文描述： 8通道，增強多格式，Δ-Σ，數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù)： 14/41頁
文件大?。?/td> 293K
代理商： DSD1608PAHR
DSD1608
SLES040
–
JUNE 2002
www.ti.com
14
DIGITAL FILTER
—
DSD MODE
f
–
Frequency
–
kHz
–
35
–
30
–
25
–
20
–
15
–
10
–
5
0
5
A
–
AMPLITUDE
vs
FREQUENCY
1
1k
10
100
Filter 3
Filter 2
Filter 1
Figure 19
SYSTEM CLOCK AND RESET FUNCTIONS
System clock input
The DSD1608 requires a system clock for operating the digital interpolation filter, digital DSD filter and multilevel
delta-sigma modulator. The system clock is applied to PSCK (pin 33) in the PCM mode and to DSCK (pin 34) in the
DSD mode. When CKCE (control register 10, B3) is not set to 1, the system clock is applied to PSCK in the DSD
mode. The DSD1608 has a system clock detection circuit. Table 1 shows examples of system clock frequencies for
common audio sampling rates.
Figure 20 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. Texas Instruments
’
PLL1700 multiclock generator is an excellent
choice for providing the DSD1608 system.
In the PCM mode, the oversampling rate of digital filter is 4
×
when a 128-f
S
or 192-f
S
system clock is applied to the
DSD1608. When a 256-f
S
, 384-f
S
, 512-f
S,
or 768-f
S
system clock is applied, the oversampling rate is 8
×
.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
MODE
SAMPLING
FREQUENCY
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
192 fS
256 fS
3.0720
4.0960
128 fS
2.0480
384 fS
6.1440
512 fS
8.1920
768 fS
12.2880
16kHz
32kHz
4.0960
6.1440
8.1920
12.2880
16.3840
24.5760
44.1kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
PCM
48kHz
6.1440
9.2160
12.2880
18.4320
24.5760
36.8640
88.2kHz
11.2896
16.9344
22.5792
33.8688
45.1584
67.7376
96kHz
12.2880
18.4320
24.5760
36.8640
49.1520
73.7280
192kHz
64
×
44.1kHz
24.5760
36.8640
See Note
See Note
See Note
See Note
DSD
—
—
11.2896
16.9344
22.5792
33.8688
NOTE:This system clock is not supported for the given sampling frequency.
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