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參數(shù)資料
| 型號： | DS1644L-150 |
| 英文描述： | Nonvolatile Timekeeping RAM |
| 中文描述： | 非易失性內(nèi)存時鐘 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | DS1644L-150 |
DS1644LPM
041697 4/11
DS1644L REGISTER MAP – BANK1
Table 2
ADDRESS
DATA
FUNCTION
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
7FFF
–
–
–
–
–
–
–
–
YEAR
00–99
7FFE
X
X
X
–
–
–
–
–
MONTH
01–12
7FFD
X
X
–
–
–
–
–
–
DATE
01–31
7FFC
X
FT
X
X
X
–
–
–
DAY
01–07
7FFB
X
X
–
–
–
–
–
–
HOUR
00–23
7FFA
X
–
–
–
–
–
–
–
MINUTES
00–59
7FF9
OSC
–
–
–
–
–
–
–
SECONDS
00–59
7FF8
W
R
X
X
X
X
X
X
CONTROL
A
OSC = STOP BIT
W
= WRITE BIT
R
X
=
=
READ BIT
UNUSED
FT =
FREQUENCY TEST
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1644L is in the read mode whenever WE (write
enable) is high, and CE (chip enable) is low. The device
architecture allows ripple-through access to any of the
address locations in the NV SRAM. Valid data will be
available at the DQ pins within t
AA
after the last address
input is stable, providing that the CE and OE access
times and states are satisfied. If CE or OE access times
are not met, valid data will be available at the latter of
chip enable access (t
CEA
) or at output enable access
time (t
OEA
). The state of the data input/output pins (DQ)
is controlled by CE and OE. If the outputs are activated
before t
AA
, the data lines are driven to an intermediate
state until t
AA
. If the address inputs are changed while
CE and OE remain valid, output data will remain valid for
output data hold time (t
OH
) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1644L is in the write mode whenever WE and
CE are in their active state. The start of a write is refer-
enced to the latter occurring high to low transition of WE
or CE. The addresses must be held valid throughout the
cycle. CE or WE must return inactive for a minimum of
t
WR
prior to the initiation of another read or write cycle.
Data in must be valid t
DS
prior to the end of write and re-
main valid for t
DH
afterward. In a typical application, the
OE signal will be high during a write cycle. However,
OE can be active provided that care is taken with the
data bus to avoid bus contention. If OE is low prior to
WE transitioning low the data bus can become active
with read data defined by the address inputs. A low tran-
sition on WE will then disable the outputs t
WEZ
after WE
goes active.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1644LPM | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Nonvolatile Timekeeping RAM |
| DS1644P | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Nonvolatile Timekeeping RAM |
| DS1644P+120 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Nonvolatile Timekeeping RAM |
| DS1644P-120 | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1644P120+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Nonvolatile Timekeeping RAM |
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