參數(shù)資料
型號： CY7C1355C-117AC
廠商： Cypress Semiconductor Corp.
英文描述： 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
中文描述： 9兆位（256 × 36/512K × 18）流體系結(jié)構(gòu)，通過與總線延遲靜態(tài)存儲器
文件頁數(shù)： 13/32頁
文件大?。?/td> 496K
代理商： CY7C1355C-117AC
PRELIMINARY
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. **
Page 13 of 33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1355C/CY7C1357C incorporates a serial boundary
scan test access port (TAP). This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or
2.5V I/O logic levels.
The CY7C1355C/CY7C1357Ccontains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V
SS
) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to V
DD
through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of the TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
相關(guān)PDF資料
PDF描述
CY7C1355C-117AI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-117BGC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-117BGI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-117BZC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-117BZI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1355C-133AXC 功能描述:靜態(tài)隨機存取存儲器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1355C-133AXCKJ 制造商:Cypress Semiconductor 功能描述:
CY7C1355C-133AXCT 功能描述:靜態(tài)隨機存取存儲器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1355C-133AXI 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C1355C-133AXIT 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
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