參數(shù)資料
型號(hào)： CY7C1354C-200AXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
中文描述： 256K X 36 ZBT SRAM, 3.2 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù)： 12/28頁(yè)
文件大小： 467K
代理商： CY7C1354C-200AXI
CY7C1354C
CY7C1356C
Document #: 38-05538 Rev. *G
Page 12 of 28
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
[10, 11]
Parameter
Clock
t
TCYC
t
TF
t
TH
t
TL
Output Times
t
TDOV
t
TDOX
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
ns
20
20
20
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
Notes:
10.t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. t
R
/t
F
= 1 ns.
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
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相關(guān)PDF資料
PDF描述
CY7C1354C-200BGC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BGI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BGXC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BGXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1354C-200BZC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1354C-200AXIKJ 制造商:Cypress Semiconductor 功能描述:
CY7C1354C-200AXIT 制造商:Cypress Semiconductor 功能描述:SYNC - Tape and Reel 制造商:Cypress Semiconductor 功能描述:IC SRAM 9MBIT 200MHZ 100TQFP 制造商:Cypress Semiconductor 功能描述:REEL / Sync SRAMs
CY7C1354C-200AXT 制造商:Cypress Semiconductor 功能描述:
CY7C1354C-200BGC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V NoBL Sync PL COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1354C-225AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V NoBL Sync PL COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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