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參數(shù)資料
| 型號(hào)： | CY7C1314BV18-250BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 512K X 36 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 9/23頁(yè) |
| 文件大?。?/td> | 262K |
| 代理商： | CY7C1314BV18-250BZC |
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PRELIMINARY
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. **
Page 9 of 23
Application Example
[1]
Truth Table
[2, 3, 4, 5, 6, 7]
Operation
K
RPS
X
WPS
L
DQ
DQ
Write Cycle:
Load address on the rising edge of K clock;
input write data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock;
wait one and a half cycle; read data on C
and C rising edges.
NOP: No Operation
L-H
D(A + 0)at K(t)
↑
D(A + 1) at K(t)
↑
L-H
L
X
Q(A + 0) at C(t + 1)
↑
Q(A + 1) at C(t + 2)
↑
L-H
H
H
D = X
Q = High-Z
Previous State
D = X
Q = High-Z
Previous State
Standby: Clock Stopped
Stopped
X
X
Write Cycle Descriptions
(CY7C1310BV18 and CY7C1312BV18)
[2, 8]
BWS
0
/
NWS
0
L
BWS
1
/
NWS
1
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence
:
CY7C1310BV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1312BV18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1310BV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1312BV18
both bytes (D
[17:0]
) are written into the device.
–
During the Data portion of a Write sequence
:
CY7C1310BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1312BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
L
L
–
L
H
L-H
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
and BWS
3
can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
C
C#
D
A
K
C
C#
D
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
R = 50
οημσ
R = 250
οημσ
R = 250
οημσ
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1910BV18 | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1310BV18-167BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1910BV18-167BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1310BV18-200BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1910BV18-200BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1314BV18-250BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 512KX36 0.45NS 165FBGA - Bulk |
| CY7C1314BV18-250BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 1.8V QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1314CV18-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 1.8V QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1314CV18-200BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 1.8V QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1314CV18-200BZI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18-Mbit QDR-II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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