颜射内射国产在线,老司机午夜资源,99精品国产99久久久久久51

收藏本站

您好，
買賣IC網(wǎng)歡迎您。
請登錄
免費注冊

您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379059 > CY7C1314BV18-250BZC (CYPRESS SEMICONDUCTOR CORP) 18-Mbit QDR-II SRAM 2-Word Burst Architecture PDF資料下載

參數(shù)資料

型號：	CY7C1314BV18-250BZC
廠商：	CYPRESS SEMICONDUCTOR CORP
元件分類：	DRAM
英文描述：	18-Mbit QDR-II SRAM 2-Word Burst Architecture
中文描述：	512K X 36 QDR SRAM, 0.45 ns, PBGA165
封裝：	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)：	7/23頁
文件大?。?/td>	262K
代理商：	CY7C1314BV18-250BZC

第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁

PRELIMINARY

CY7C1310BV18

CY7C1910BV18

CY7C1312BV18

CY7C1314BV18

Document #: 38-05619 Rev. **

Page 7 of 23

Functional Overview

The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18 and

CY7C1314BV18 are synchronous pipelined Burst SRAMs

equipped with both a Read port and a Write port. The Read

port is dedicated to Read operations and the Write port is

dedicated to Write operations. Data flows into the SRAM

through the Write port and out through the Read port. These

devices multiplex the address inputs in order to minimize the

number of address pins required. By having separate Read

and Write ports, the QDR-II completely eliminates the need to

“turn-around” the data bus and avoids any possible data

contention, thereby simplifying system design. Each access

consists of two 8-bit data transfers in the case of

CY7C1310BV18, two 9-bit data transfers in the case of

CY7C1910BV18,two 18-bit data transfers in the case of

CY7C1312BV18 and two 36-bit data transfers in the case of

CY7C1314BV18, in one clock cycle.

Accesses for both ports are initiated on the rising edge of the

positive Input Clock (K). All synchronous input timings are

referenced from the rising edge of the input clocks (K and K)

and all output timings are referenced to the rising edge of

output clocks (C and C or K and K when in single clock mode).

All synchronous data inputs (D

[x:0]

) inputs pass through input

registers controlled by the input clocks (K and K). All

synchronous data outputs (Q

[x:0]

) outputs pass through output

registers controlled by the rising edge of the output clocks (C

and C or K and K when in single clock mode).

All synchronous control (RPS, WPS, BWS

[x:0]

) inputs pass

through input registers controlled by the rising edge of the

input clocks (K and K).

CY7C1312BV18 is described in the following sections. The

same

basic

descriptions

CY7C1910BV18 and CY7C1314BV18.

apply

CY7C1310BV18

Read Operations

The CY7C1312BV18 is organized internally as 2 arrays of

512K x 18. Accesses are completed in a burst of two

sequential 18-bit data words. Read operations are initiated by

Input-Clock

Negative Input Clock Input

. K is used to capture synchronous inputs being presented

to the device and to drive out data through Q

[x:0]

when in single clock mode.

CQ is referenced with respect to C

. This is a free running clock and is synchronized

to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with

respect to K. The timings for the echo clocks are shown in the AC Timing table.

CQ is referenced with respect to C

. This is a free running clock and is synchronized

to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with

respect to K. The timings for the echo clocks are shown in the AC Timing table.

Output Impedance Matching Input

. This input is used to tune the device outputs to the

system data bus impedance. CQ, CQ, and Q

[x:0]

output impedance are set to 0.2 x RQ,

where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be

connected directly to V

, which enables the minimum impedance mode. This pin cannot

be connected directly to GND or left unconnected.

DLL Turn Off, active LOW

. Connecting this pin to ground will turn off the DLL inside the

device. The timings in the DLL turned off operation will be different from those listed in

this data sheet. More details on this operation can be found in the application note, “DLL

Operation in the QDR-II.”

TDO for JTAG

TCK pin for JTAG

TDI pin for JTAG

TMS pin for JTAG

Not connected to the die