參數(shù)資料
型號： CY7C1314BV18-250BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit QDR-II SRAM 2-Word Burst Architecture
中文描述： 512K X 36 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)： 10/23頁
文件大小： 262K
代理商： CY7C1314BV18-250BZC
PRELIMINARY
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. **
Page 10 of 23
L
H
–
L-H During the Data portion of a Write sequence
:
CY7C1310BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1312BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
–
During the Data portion of a Write sequence
:
CY7C1310BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1312BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
L-H During the Data portion of a Write sequence
:
CY7C1310BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1312BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
H
L
L-H
H
L
–
H
H
H
H
L-H
–
Write Cycle Descriptions
(CY7C1314BV18)
[2, 8]
BWS
0
BWS
1
L
BWS
2
L
BWS
3
L
K
K
-
Comments
L
L-H
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written
into the device.
L-H During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written
into the device.
-
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
-
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
-
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
will remain unaltered.
-
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
L
L
L
L
-
L
H
H
H
L-H
L
H
H
H
-
H
L
H
H
L-H
H
L
H
H
-
H
H
L
H
L-H
H
H
L
H
-
H
H
H
L
L-H
H
H
H
L
-
H
H
H
H
H
H
H
H
L-H
-
Write Cycle Descriptions
(CY7C1910BV18)
BWS
0
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence
:
CY7C1910BV18
the single byte
(D
[8:0]
) is written into the device
During the Data portion of a Write sequence
:
CY7C1910BV18
the single byte
(D
[8:0]
) is written into the device,
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L
–
L-H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1310BV18 and CY7C1312BV18) (continued)
[2, 8]
BWS
0
/
NWS
0
BWS
1
/
NWS
1
K
K
Comments
相關(guān)PDF資料
PDF描述
CY7C1910BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1310BV18-167BZC 18-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1910BV18-167BZC 18-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1310BV18-200BZC 18-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1910BV18-200BZC 18-Mbit QDR-II SRAM 2-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1314BV18-250BZCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 512KX36 0.45NS 165FBGA - Bulk
CY7C1314BV18-250BZXC 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1314CV18-167BZC 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1314CV18-200BZC 功能描述:靜態(tài)隨機(jī)存取存儲器 512Kx36 1.8V QDR II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1314CV18-200BZI 功能描述:靜態(tài)隨機(jī)存取存儲器 18-Mbit QDR-II 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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